[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41081 )

Change subject: soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options
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soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options

Intel introduced the UPD VrPowerDeliveryDesign with Cannon Lake. The
BIOS needs to program VrPowerDeliverDesign configuration per platform
according to the platform capabilities to avoid incorrect
electrial/power parameters. This is only added for Cannon Lake.

Refer to document 599797 for more details.

Change-Id: I89b8dceb40fa6a9dc67b218e91bf728ff928b5a0
Signed-off-by: Christian Walter 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41081
Reviewed-by: Philipp Deppenwiese 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Philipp Deppenwiese: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 4f015a7..f6ec7ce 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -413,6 +413,10 @@
    uint8_t LanWakeFromDeepSx;
    uint8_t WolEnableOverride;

+#if !CONFIG(SOC_INTEL_COMETLAKE)
+	uint32_t VrPowerDeliveryDesign;
+#endif
+
    /*
     * Override GPIO PM configuration:
     * 0: Use FSP default GPIO PM program,
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index b432087..b7e9ad8 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -459,6 +459,10 @@
 #endif
    }

+#if !CONFIG(SOC_INTEL_COMETLAKE)
+	params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign;
+#endif
+
    dev = pcidev_path_on_root(SA_DEVFN_IGD);
    if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
    	params->PeiGraphicsPeimInit = 1;