[coreboot-gerrit] Change in coreboot[master]: mb/intel/jasperlake_rvp: Disable SATA controller

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38996 )

Change subject: mb/intel/jasperlake_rvp: Disable SATA controller
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mb/intel/jasperlake_rvp: Disable SATA controller

This patch disables the SATA config from devicetree for JSL RVP, since we
are not planning to use the SATA storage in chrome config.

Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2
Signed-off-by: Usha P 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38996
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
Reviewed-by: V Sowmya 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
1 file changed, 2 insertions(+), 20 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  V Sowmya: Looks good to me, approved

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 843de14..9c40f66 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -66,25 +66,7 @@
    # ClkReq-to-ClkSrc mapping for CLK SRC 0
    register "PcieClkSrcClkReq[0]" = "0x00"

-	register "SataEnable" = "1"
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"
-	register "SataPortsEnable[2]" = "1"
-	register "SataPortsEnable[3]" = "1"
-	register "SataPortsEnable[4]" = "1"
-	register "SataPortsEnable[5]" = "1"
-	register "SataPortsEnable[6]" = "1"
-	register "SataPortsEnable[7]" = "1"
-
-	register "SataPortsDevSlp[0]" = "1"
-	register "SataPortsDevSlp[1]" = "1"
-	register "SataPortsDevSlp[2]" = "1"
-	register "SataPortsDevSlp[3]" = "1"
-	register "SataPortsDevSlp[4]" = "1"
-	register "SataPortsDevSlp[5]" = "1"
-	register "SataPortsDevSlp[6]" = "1"
-	register "SataPortsDevSlp[7]" = "1"
+	register "SataEnable" = "0"

register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoPci,
@@ -256,7 +238,7 @@
    	device pci 16.3 off end # Management Engine KT Redirection
    	device pci 16.4 off end # Management Engine Interface 3
    	device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on  end # SATA
+		device pci 17.0 off end # SATA
    	device pci 19.0 on  end # I2C #4
    	device pci 19.1 off end # I2C #5
    	device pci 19.2 on  end # UART #2