Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13657
-gerrit
commit 0bb4aae0c95b271f5d5be580cf4b6712e12186c2 Author: Vladimir Serbinenko phcoder@gmail.com Date: Wed Feb 10 01:43:08 2016 +0100
Move gpio.h to gpio.c on sandy and ivy.
Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/mainboard/google/link/Makefile.inc | 1 + src/mainboard/google/link/gpio.c | 119 +++++++++ src/mainboard/google/link/gpio.h | 119 --------- src/mainboard/google/link/romstage.c | 3 +- src/mainboard/google/parrot/Makefile.inc | 1 + src/mainboard/google/parrot/gpio.c | 275 +++++++++++++++++++++ src/mainboard/google/parrot/gpio.h | 275 --------------------- src/mainboard/google/parrot/romstage.c | 2 - src/mainboard/google/stout/Makefile.inc | 1 + src/mainboard/google/stout/gpio.c | 288 ++++++++++++++++++++++ src/mainboard/google/stout/gpio.h | 288 ---------------------- src/mainboard/google/stout/romstage.c | 2 - src/mainboard/intel/emeraldlake2/Makefile.inc | 1 + src/mainboard/intel/emeraldlake2/gpio.c | 102 ++++++++ src/mainboard/intel/emeraldlake2/gpio.h | 102 -------- src/mainboard/intel/emeraldlake2/romstage.c | 2 - src/mainboard/kontron/ktqm77/Makefile.inc | 1 + src/mainboard/kontron/ktqm77/gpio.c | 299 +++++++++++++++++++++++ src/mainboard/kontron/ktqm77/gpio.h | 299 ----------------------- src/mainboard/kontron/ktqm77/romstage.c | 2 - src/mainboard/samsung/lumpy/Makefile.inc | 1 + src/mainboard/samsung/lumpy/gpio.c | 332 ++++++++++++++++++++++++++ src/mainboard/samsung/lumpy/gpio.h | 332 -------------------------- src/mainboard/samsung/lumpy/romstage.c | 2 - src/mainboard/samsung/stumpy/Makefile.inc | 1 + src/mainboard/samsung/stumpy/gpio.c | 306 ++++++++++++++++++++++++ src/mainboard/samsung/stumpy/gpio.h | 306 ------------------------ src/mainboard/samsung/stumpy/romstage.c | 2 - 28 files changed, 1729 insertions(+), 1735 deletions(-)
diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index c366b08..b79e4d3 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -42,3 +42,4 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := spd +romstage-y += gpio.c diff --git a/src/mainboard/google/link/gpio.c b/src/mainboard/google/link/gpio.c new file mode 100644 index 0000000..ea6110e --- /dev/null +++ b/src/mainboard/google/link/gpio.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LINK_GPIO_H +#define LINK_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ + .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ + .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ + .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ + .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ + .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ + .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ + .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ + .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ + .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ + .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ + .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ + .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ + .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio1 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ + .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ + .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ + .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio36 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/google/link/gpio.h b/src/mainboard/google/link/gpio.h deleted file mode 100644 index ea6110e..0000000 --- a/src/mainboard/google/link/gpio.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LINK_GPIO_H -#define LINK_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ - .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ - .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ - .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ - .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ - .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ - .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ - .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ - .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ - .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ - .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ - .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ - .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ - .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio28 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio1 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio12 = GPIO_INVERT, - .gpio14 = GPIO_INVERT, - .gpio15 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ - .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ - .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ - .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio36 = GPIO_DIR_OUTPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio36 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f40ba5..5710ccd 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -29,13 +29,12 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/gpio.h> +#include <southbridge/intel/bd82x6x/pch.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #include <tpm.h> #include <cbfs.h>
diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 0d6ef2e..78e5b98 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -17,3 +17,4 @@ ramstage-y += ec.c
romstage-y += chromeos.c ramstage-y += chromeos.c +romstage-y += gpio.c diff --git a/src/mainboard/google/parrot/gpio.c b/src/mainboard/google/parrot/gpio.c new file mode 100644 index 0000000..c3e3e2f --- /dev/null +++ b/src/mainboard/google/parrot/gpio.c @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef PARROT_GPIO_H +#define PARROT_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NONE, /* NOT USED */ + .gpio1 = GPIO_MODE_NONE, /* NOT USED */ + .gpio2 = GPIO_MODE_NATIVE, /* NOT USED / PIRQE# */ + .gpio3 = GPIO_MODE_NONE, /* NOT USED / PIRQ#F */ + .gpio4 = GPIO_MODE_NONE, /* NOT USED / PIRQG# */ + .gpio5 = GPIO_MODE_NONE, /* NOT USED / PIRQH# */ + .gpio6 = GPIO_MODE_NONE, /* NOT USED / FAN TACH2 */ + .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ + .gpio8 = GPIO_MODE_GPIO, /* EC SMI# */ + .gpio9 = GPIO_MODE_NATIVE, /* NOT USED / OC5# USB */ + .gpio10 = GPIO_MODE_NATIVE, /* NOT USED / OC6# USB */ + .gpio11 = GPIO_MODE_NONE, /* NOT USED / SMB_ALERT*/ + .gpio12 = GPIO_MODE_GPIO, /* Track Pad IRQ / LAN_PHY_PWR_CTRL / SMB_ALERT */ + .gpio13 = GPIO_MODE_NONE, /* NOT USED / HDA_DOCK_RST */ + .gpio14 = GPIO_MODE_NATIVE, /* NOT USED / OC7# USB */ + .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT (INPUT to PantherPoint) */ + .gpio16 = GPIO_MODE_NONE, /* NOT USED / SATA4GP */ + .gpio17 = GPIO_MODE_GPIO, /* DEV MODE */ + .gpio18 = GPIO_MODE_NATIVE, /* PCIECLKRQ1# */ + .gpio19 = GPIO_MODE_NONE, /* BIOS BOOT STRAP (NOT USED)/ SATA1GP */ + .gpio20 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ2# */ + .gpio21 = GPIO_MODE_NONE, /* NOT USED / SATA0GP */ + .gpio22 = GPIO_MODE_NONE, /* NOT USED */ + .gpio23 = GPIO_MODE_NONE, /* NOT USED */ + .gpio24 = GPIO_MODE_NONE, /* NOT USED / MEM_LED */ + .gpio25 = GPIO_MODE_NATIVE, /* PCIECLKRQ3# */ + .gpio26 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ4# */ + .gpio27 = GPIO_MODE_NONE, /* S4,S5 WAKE? */ + .gpio28 = GPIO_MODE_NONE, /* On-Die PLL Voltage Regulator */ + .gpio29 = GPIO_MODE_NONE, /* NOT USED / SLP_LAN# */ + .gpio30 = GPIO_MODE_NATIVE, /* SUS_WARN# */ + .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_LOW, + .gpio30 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ + .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ + .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ + .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_LOW, + .gpio59 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_LOW, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX0 */ + .gpio65 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX1 */ + .gpio66 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX2 */ + .gpio67 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX3 */ + .gpio68 = GPIO_MODE_NONE, /* NOT USED / FAN TACK4 */ + .gpio69 = GPIO_MODE_GPIO, /* REC_MODE_L / FAN TACK5 */ + .gpio70 = GPIO_MODE_GPIO, /* SPI_WP1#_RPCH / FAN TACK7 */ + .gpio71 = GPIO_MODE_GPIO, /* LVDS/eDP / FAN TACK8 */ + .gpio72 = GPIO_MODE_NONE, /* NOT USED / BATLOW# */ + .gpio73 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ0#*/ + .gpio74 = GPIO_MODE_NONE, /* NOT USED / SML1ALERT# /PCHHOT# */ + .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_LOW, + .gpio75 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/google/parrot/gpio.h b/src/mainboard/google/parrot/gpio.h deleted file mode 100644 index c3e3e2f..0000000 --- a/src/mainboard/google/parrot/gpio.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PARROT_GPIO_H -#define PARROT_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_NONE, /* NOT USED */ - .gpio1 = GPIO_MODE_NONE, /* NOT USED */ - .gpio2 = GPIO_MODE_NATIVE, /* NOT USED / PIRQE# */ - .gpio3 = GPIO_MODE_NONE, /* NOT USED / PIRQ#F */ - .gpio4 = GPIO_MODE_NONE, /* NOT USED / PIRQG# */ - .gpio5 = GPIO_MODE_NONE, /* NOT USED / PIRQH# */ - .gpio6 = GPIO_MODE_NONE, /* NOT USED / FAN TACH2 */ - .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ - .gpio8 = GPIO_MODE_GPIO, /* EC SMI# */ - .gpio9 = GPIO_MODE_NATIVE, /* NOT USED / OC5# USB */ - .gpio10 = GPIO_MODE_NATIVE, /* NOT USED / OC6# USB */ - .gpio11 = GPIO_MODE_NONE, /* NOT USED / SMB_ALERT*/ - .gpio12 = GPIO_MODE_GPIO, /* Track Pad IRQ / LAN_PHY_PWR_CTRL / SMB_ALERT */ - .gpio13 = GPIO_MODE_NONE, /* NOT USED / HDA_DOCK_RST */ - .gpio14 = GPIO_MODE_NATIVE, /* NOT USED / OC7# USB */ - .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT (INPUT to PantherPoint) */ - .gpio16 = GPIO_MODE_NONE, /* NOT USED / SATA4GP */ - .gpio17 = GPIO_MODE_GPIO, /* DEV MODE */ - .gpio18 = GPIO_MODE_NATIVE, /* PCIECLKRQ1# */ - .gpio19 = GPIO_MODE_NONE, /* BIOS BOOT STRAP (NOT USED)/ SATA1GP */ - .gpio20 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ2# */ - .gpio21 = GPIO_MODE_NONE, /* NOT USED / SATA0GP */ - .gpio22 = GPIO_MODE_NONE, /* NOT USED */ - .gpio23 = GPIO_MODE_NONE, /* NOT USED */ - .gpio24 = GPIO_MODE_NONE, /* NOT USED / MEM_LED */ - .gpio25 = GPIO_MODE_NATIVE, /* PCIECLKRQ3# */ - .gpio26 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ4# */ - .gpio27 = GPIO_MODE_NONE, /* S4,S5 WAKE? */ - .gpio28 = GPIO_MODE_NONE, /* On-Die PLL Voltage Regulator */ - .gpio29 = GPIO_MODE_NONE, /* NOT USED / SLP_LAN# */ - .gpio30 = GPIO_MODE_NATIVE, /* SUS_WARN# */ - .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_INPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_INPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_OUTPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_LOW, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_LOW, - .gpio8 = GPIO_LEVEL_LOW, - .gpio9 = GPIO_LEVEL_LOW, - .gpio10 = GPIO_LEVEL_LOW, - .gpio11 = GPIO_LEVEL_LOW, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - .gpio14 = GPIO_LEVEL_LOW, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_LOW, - .gpio19 = GPIO_LEVEL_LOW, - .gpio20 = GPIO_LEVEL_LOW, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_LOW, - .gpio23 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_LOW, - .gpio26 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_LOW, - .gpio30 = GPIO_LEVEL_LOW, - .gpio31 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio12 = GPIO_INVERT, - .gpio15 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ - .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ - .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ - .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_INPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_INPUT, - .gpio47 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_INPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_INPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_INPUT, - .gpio56 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_INPUT, - .gpio61 = GPIO_DIR_INPUT, - .gpio62 = GPIO_DIR_INPUT, - .gpio63 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_LOW, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_LOW, - .gpio41 = GPIO_LEVEL_LOW, - .gpio42 = GPIO_LEVEL_LOW, - .gpio43 = GPIO_LEVEL_LOW, - .gpio44 = GPIO_LEVEL_LOW, - .gpio45 = GPIO_LEVEL_LOW, - .gpio46 = GPIO_LEVEL_LOW, - .gpio47 = GPIO_LEVEL_LOW, - .gpio48 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_LOW, - .gpio50 = GPIO_LEVEL_LOW, - .gpio51 = GPIO_LEVEL_LOW, - .gpio52 = GPIO_LEVEL_LOW, - .gpio53 = GPIO_LEVEL_LOW, - .gpio54 = GPIO_LEVEL_LOW, - .gpio55 = GPIO_LEVEL_LOW, - .gpio56 = GPIO_LEVEL_LOW, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_LOW, - .gpio59 = GPIO_LEVEL_LOW, - .gpio60 = GPIO_LEVEL_LOW, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX0 */ - .gpio65 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX1 */ - .gpio66 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX2 */ - .gpio67 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX3 */ - .gpio68 = GPIO_MODE_NONE, /* NOT USED / FAN TACK4 */ - .gpio69 = GPIO_MODE_GPIO, /* REC_MODE_L / FAN TACK5 */ - .gpio70 = GPIO_MODE_GPIO, /* SPI_WP1#_RPCH / FAN TACK7 */ - .gpio71 = GPIO_MODE_GPIO, /* LVDS/eDP / FAN TACK8 */ - .gpio72 = GPIO_MODE_NONE, /* NOT USED / BATLOW# */ - .gpio73 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ0#*/ - .gpio74 = GPIO_MODE_NONE, /* NOT USED / SML1ALERT# /PCHHOT# */ - .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, - .gpio65 = GPIO_DIR_INPUT, - .gpio66 = GPIO_DIR_INPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_INPUT, - .gpio71 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio73 = GPIO_DIR_INPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_LOW, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_LOW, - .gpio71 = GPIO_LEVEL_LOW, - .gpio72 = GPIO_LEVEL_LOW, - .gpio73 = GPIO_LEVEL_LOW, - .gpio74 = GPIO_LEVEL_LOW, - .gpio75 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 60c3f01..030f7c4 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -29,11 +29,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #include <cbfs.h> #include <tpm.h> #include "ec/compal/ene932/ec.h" diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 256948d..f151e4f 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -22,3 +22,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c
SRC_ROOT = $(src)/mainboard/google/stout +romstage-y += gpio.c diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c new file mode 100644 index 0000000..7fffe8b --- /dev/null +++ b/src/mainboard/google/stout/gpio.c @@ -0,0 +1,288 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STOUT_GPIO_H +#define STOUT_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ + .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ + .gpio2 = GPIO_MODE_NONE, /* NOT USED */ + .gpio3 = GPIO_MODE_NONE, /* NOT USED */ + .gpio4 = GPIO_MODE_NONE, /* NOT USED */ + .gpio5 = GPIO_MODE_GPIO, /* INTH# */ + .gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */ + .gpio7 = GPIO_MODE_GPIO, /* GE_SCR_WP# */ + .gpio8 = GPIO_MODE_NONE, /* NOT USED */ + .gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */ + .gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */ + .gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */ + .gpio12 = GPIO_MODE_GPIO, /* GPIO12 */ + .gpio13 = GPIO_MODE_GPIO, /* GPIO13 */ + .gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */ + .gpio15 = GPIO_MODE_GPIO, /* GPIO15 */ + .gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */ + .gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */ + .gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */ + .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */ + .gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */ + .gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */ + .gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */ + .gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */ + .gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */ + .gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */ + .gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */ + .gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */ + .gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */ + .gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */ + .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */ + .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + + .gpio19 = GPIO_DIR_OUTPUT, + + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_OUTPUT, + + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + + .gpio19 = GPIO_LEVEL_LOW, + + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ + .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ + .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ + .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ + .gpio36 = GPIO_MODE_NONE, /* NOT USED */ + .gpio37 = GPIO_MODE_NONE, /* NOT USED */ + .gpio38 = GPIO_MODE_NONE, /* NOT USED */ + .gpio39 = GPIO_MODE_NONE, /* NOT USED */ + .gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */ + .gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */ + .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ + .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ + .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ + .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ + .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ + .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ + .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ + .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ + .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ + .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */ + .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ + .gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */ + .gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */ + .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ + .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ + .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ + .gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ + .gpio61 = GPIO_MODE_GPIO, /* LPCPD# */ + .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ + .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + + .gpio51 = GPIO_DIR_OUTPUT, + + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + + .gpio57 = GPIO_DIR_INPUT, + + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_LOW, + + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, + + .gpio51 = GPIO_LEVEL_HIGH, + + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + + .gpio57 = GPIO_LEVEL_LOW, + + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ + .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ + .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ + .gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */ + .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ + .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ + .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ + .gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */ + .gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */ + .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */ + .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ + .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h deleted file mode 100644 index 7fffe8b..0000000 --- a/src/mainboard/google/stout/gpio.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef STOUT_GPIO_H -#define STOUT_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ - .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ - .gpio2 = GPIO_MODE_NONE, /* NOT USED */ - .gpio3 = GPIO_MODE_NONE, /* NOT USED */ - .gpio4 = GPIO_MODE_NONE, /* NOT USED */ - .gpio5 = GPIO_MODE_GPIO, /* INTH# */ - .gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */ - .gpio7 = GPIO_MODE_GPIO, /* GE_SCR_WP# */ - .gpio8 = GPIO_MODE_NONE, /* NOT USED */ - .gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */ - .gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */ - .gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */ - .gpio12 = GPIO_MODE_GPIO, /* GPIO12 */ - .gpio13 = GPIO_MODE_GPIO, /* GPIO13 */ - .gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */ - .gpio15 = GPIO_MODE_GPIO, /* GPIO15 */ - .gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */ - .gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */ - .gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */ - .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */ - .gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */ - .gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */ - .gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */ - .gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */ - .gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */ - .gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */ - .gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */ - .gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */ - .gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */ - .gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */ - .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */ - .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_OUTPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - - .gpio12 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_OUTPUT, - - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_OUTPUT, - .gpio17 = GPIO_DIR_OUTPUT, - - .gpio19 = GPIO_DIR_OUTPUT, - - .gpio21 = GPIO_DIR_OUTPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_OUTPUT, - - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_LOW, - - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio17 = GPIO_LEVEL_LOW, - - .gpio19 = GPIO_LEVEL_LOW, - - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_LOW, - .gpio23 = GPIO_LEVEL_LOW, - - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_HIGH, - .gpio29 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ - .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ - .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ - .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ - .gpio36 = GPIO_MODE_NONE, /* NOT USED */ - .gpio37 = GPIO_MODE_NONE, /* NOT USED */ - .gpio38 = GPIO_MODE_NONE, /* NOT USED */ - .gpio39 = GPIO_MODE_NONE, /* NOT USED */ - .gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */ - .gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */ - .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ - .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ - .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ - .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ - .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ - .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ - .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ - .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ - .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ - .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */ - .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ - .gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */ - .gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */ - .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ - .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ - .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ - .gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ - .gpio61 = GPIO_MODE_GPIO, /* LPCPD# */ - .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ - .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - - .gpio48 = GPIO_DIR_OUTPUT, - .gpio49 = GPIO_DIR_INPUT, - - .gpio51 = GPIO_DIR_OUTPUT, - - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - - .gpio57 = GPIO_DIR_INPUT, - - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_HIGH, - .gpio35 = GPIO_LEVEL_HIGH, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_LOW, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_HIGH, - .gpio41 = GPIO_LEVEL_LOW, - - .gpio48 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_HIGH, - - .gpio51 = GPIO_LEVEL_HIGH, - - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_LOW, - - .gpio57 = GPIO_LEVEL_LOW, - - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ - .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ - .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ - .gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */ - .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ - .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ - .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ - .gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */ - .gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */ - .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */ - .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ - .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio64 = GPIO_DIR_OUTPUT, - .gpio65 = GPIO_DIR_OUTPUT, - .gpio66 = GPIO_DIR_OUTPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_OUTPUT, - .gpio70 = GPIO_DIR_OUTPUT, - .gpio71 = GPIO_DIR_OUTPUT, - .gpio72 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio64 = GPIO_LEVEL_HIGH, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_HIGH, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_HIGH, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, - .gpio72 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 99979e9..d7046a3 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -29,11 +29,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #include <bootmode.h> #include <tpm.h> #include <cbfs.h> diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index c29b1001..b3bf53f 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -15,3 +15,4 @@
romstage-y += chromeos.c ramstage-y += chromeos.c +romstage-y += gpio.c diff --git a/src/mainboard/intel/emeraldlake2/gpio.c b/src/mainboard/intel/emeraldlake2/gpio.c new file mode 100644 index 0000000..37b2430 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/gpio.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EMERALDLAKE2_GPIO_H +#define EMERALDLAKE2_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio48 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif diff --git a/src/mainboard/intel/emeraldlake2/gpio.h b/src/mainboard/intel/emeraldlake2/gpio.h deleted file mode 100644 index 37b2430..0000000 --- a/src/mainboard/intel/emeraldlake2/gpio.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef EMERALDLAKE2_GPIO_H -#define EMERALDLAKE2_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, - .gpio1 = GPIO_MODE_GPIO, - .gpio3 = GPIO_MODE_GPIO, - .gpio5 = GPIO_MODE_GPIO, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_GPIO, - .gpio12 = GPIO_MODE_GPIO, - .gpio15 = GPIO_MODE_GPIO, - .gpio21 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio24 = GPIO_MODE_GPIO, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, - .gpio48 = GPIO_MODE_GPIO, - .gpio57 = GPIO_MODE_GPIO, - .gpio60 = GPIO_MODE_GPIO, -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio48 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; - -#endif diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 145526a..8528bff 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -30,12 +30,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> #include <tpm.h> -#include "gpio.h"
#define SIO_PORT 0x164e
diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/kontron/ktqm77/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/kontron/ktqm77/gpio.c b/src/mainboard/kontron/ktqm77/gpio.c new file mode 100644 index 0000000..a6c3960 --- /dev/null +++ b/src/mainboard/kontron/ktqm77/gpio.c @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef KTQM77_GPIO_H +#define KTQM77_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +/* + * TODO: Investigate somehow... Current values are taken from a running + * system with vendor supplied firmware. + */ + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio1 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio2 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio3 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio4 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio5 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio6 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio7 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio8 = GPIO_MODE_GPIO, /* Unknown Output LOW*/ + .gpio9 = GPIO_MODE_NATIVE, /* Native - OC5# pin */ + .gpio10 = GPIO_MODE_NATIVE, /* Native - OC6# pin */ + .gpio11 = GPIO_MODE_NATIVE, /* Native - SMBALERT# pin */ + .gpio12 = GPIO_MODE_NATIVE, /* Native - LAN_PHY_PWR_CTRL */ + .gpio13 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio14 = GPIO_MODE_NATIVE, /* Native - OC7# pin */ + .gpio15 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio16 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio17 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin */ + .gpio19 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio20 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio21 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio22 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio23 = GPIO_MODE_NATIVE, /* Native - LDRQ1# pin */ + .gpio24 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio25 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio26 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ4# pin */ + .gpio27 = GPIO_MODE_GPIO, /* Unknown Input */ /* Vendor supplied DSDT sets this conditionally + when going to suspend (S3, S4, S5). */ + .gpio28 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio29 = GPIO_MODE_NATIVE, /* Native - SLP_LAN# pin, forced by soft strap */ + .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# pin */ + .gpio31 = GPIO_MODE_NATIVE /* Native - ACPRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio1 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio2 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio3 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio4 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio5 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio6 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio7 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio8 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio9 = GPIO_DIR_INPUT, /* Native */ + .gpio10 = GPIO_DIR_INPUT, /* Native */ + .gpio11 = GPIO_DIR_INPUT, /* Native */ + .gpio12 = GPIO_DIR_INPUT, /* Native */ + .gpio13 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio14 = GPIO_DIR_INPUT, /* Native */ + .gpio15 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio16 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio17 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio18 = GPIO_DIR_INPUT, /* Native */ + .gpio19 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio20 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio21 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio22 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio23 = GPIO_DIR_INPUT, /* Native */ + .gpio24 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio25 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio26 = GPIO_DIR_INPUT, /* Native */ + .gpio27 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio28 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio29 = GPIO_DIR_INPUT, /* Native */ + .gpio30 = GPIO_DIR_INPUT, /* Native */ + .gpio31 = GPIO_DIR_INPUT, /* Native */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio1 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio2 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio3 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio4 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio5 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio6 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio7 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio8 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio9 = GPIO_LEVEL_LOW, /* Native */ + .gpio10 = GPIO_LEVEL_LOW, /* Native */ + .gpio11 = GPIO_LEVEL_LOW, /* Native */ + .gpio12 = GPIO_LEVEL_LOW, /* Native */ + .gpio13 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio14 = GPIO_LEVEL_LOW, /* Native */ + .gpio15 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio16 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio17 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio18 = GPIO_LEVEL_LOW, /* Native */ + .gpio19 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio20 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio21 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio22 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio23 = GPIO_LEVEL_LOW, /* Native */ + .gpio24 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio25 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio26 = GPIO_LEVEL_LOW, /* Native */ + .gpio27 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio28 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio29 = GPIO_LEVEL_LOW, /* Native */ + .gpio30 = GPIO_LEVEL_LOW, /* Native */ + .gpio31 = GPIO_LEVEL_LOW, /* Native */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* Native - CLKRUN# pin */ + .gpio33 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio34 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio35 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio36 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio37 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio38 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio39 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio40 = GPIO_MODE_NATIVE, /* Native - OC1# pin */ + .gpio41 = GPIO_MODE_NATIVE, /* Native - OC2# pin */ + .gpio42 = GPIO_MODE_NATIVE, /* Native - OC3# pin */ + .gpio43 = GPIO_MODE_NATIVE, /* Native - OC4# pin */ + .gpio44 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ5# pin */ + .gpio45 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ6# pin */ + .gpio46 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ7# pin */ + .gpio47 = GPIO_MODE_NATIVE, /* Native - PEG_A_CLKRQ# pin */ + .gpio48 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio49 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio50 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio51 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio52 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio53 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio54 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio55 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio56 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio57 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio58 = GPIO_MODE_NATIVE, /* Native - SML1CLK */ + .gpio59 = GPIO_MODE_NATIVE, /* Native - OC0# pin */ + .gpio60 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio61 = GPIO_MODE_NATIVE, /* Native - SUS_STAT# pin*/ + .gpio62 = GPIO_MODE_NATIVE, /* Native - SUSCLK */ + .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5# */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, /* Native */ + .gpio33 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio34 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio35 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio36 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio37 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio38 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio39 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio40 = GPIO_DIR_INPUT, /* Native */ + .gpio41 = GPIO_DIR_INPUT, /* Native */ + .gpio42 = GPIO_DIR_INPUT, /* Native */ + .gpio43 = GPIO_DIR_INPUT, /* Native */ + .gpio44 = GPIO_DIR_INPUT, /* Native */ + .gpio45 = GPIO_DIR_INPUT, /* Native */ + .gpio46 = GPIO_DIR_INPUT, /* Native */ + .gpio47 = GPIO_DIR_INPUT, /* Native */ + .gpio48 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio49 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio50 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio51 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio52 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio53 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio54 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio55 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio56 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio57 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio58 = GPIO_DIR_INPUT, /* Native */ + .gpio59 = GPIO_DIR_INPUT, /* Native */ + .gpio60 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio61 = GPIO_DIR_INPUT, /* Native */ + .gpio62 = GPIO_DIR_INPUT, /* Native */ + .gpio63 = GPIO_DIR_INPUT, /* Native */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, /* Native */ + .gpio33 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio34 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio35 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio36 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio37 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio38 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio39 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio40 = GPIO_LEVEL_LOW, /* Native */ + .gpio41 = GPIO_LEVEL_LOW, /* Native */ + .gpio42 = GPIO_LEVEL_LOW, /* Native */ + .gpio43 = GPIO_LEVEL_LOW, /* Native */ + .gpio44 = GPIO_LEVEL_LOW, /* Native */ + .gpio45 = GPIO_LEVEL_LOW, /* Native */ + .gpio46 = GPIO_LEVEL_LOW, /* Native */ + .gpio47 = GPIO_LEVEL_LOW, /* Native */ + .gpio48 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio49 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio50 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio51 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio52 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio53 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio54 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio55 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio56 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio57 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio58 = GPIO_LEVEL_LOW, /* Native */ + .gpio59 = GPIO_LEVEL_LOW, /* Native */ + .gpio60 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio61 = GPIO_LEVEL_LOW, /* Native */ + .gpio62 = GPIO_LEVEL_LOW, /* Native */ + .gpio63 = GPIO_LEVEL_LOW, /* Native */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio65 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio66 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio67 = GPIO_MODE_NATIVE, /* Native - CLKOUTFLEX3 */ + .gpio68 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio69 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio70 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio71 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio72 = GPIO_MODE_NATIVE, /* Native - nothing on mobile */ + .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# pin */ + .gpio74 = GPIO_MODE_NATIVE, /* Native - SML1ALERT#/PCHHOT# pin */ + .gpio75 = GPIO_MODE_NATIVE, /* Native - SML1DATA */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio65 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio67 = GPIO_DIR_INPUT, /* Native */ + .gpio68 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio69 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio70 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio71 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio72 = GPIO_DIR_INPUT, /* Native */ + .gpio73 = GPIO_DIR_INPUT, /* Native */ + .gpio74 = GPIO_DIR_INPUT, /* Native */ + .gpio75 = GPIO_DIR_INPUT, /* Native */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio65 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio66 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio67 = GPIO_LEVEL_LOW, /* Native */ + .gpio68 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio69 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio70 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio71 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio72 = GPIO_LEVEL_LOW, /* Native */ + .gpio73 = GPIO_LEVEL_LOW, /* Native */ + .gpio74 = GPIO_LEVEL_LOW, /* Native */ + .gpio75 = GPIO_LEVEL_LOW, /* Native */ +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/kontron/ktqm77/gpio.h b/src/mainboard/kontron/ktqm77/gpio.h deleted file mode 100644 index a6c3960..0000000 --- a/src/mainboard/kontron/ktqm77/gpio.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef KTQM77_GPIO_H -#define KTQM77_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -/* - * TODO: Investigate somehow... Current values are taken from a running - * system with vendor supplied firmware. - */ - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio1 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio2 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio3 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio4 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio5 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio6 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio7 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio8 = GPIO_MODE_GPIO, /* Unknown Output LOW*/ - .gpio9 = GPIO_MODE_NATIVE, /* Native - OC5# pin */ - .gpio10 = GPIO_MODE_NATIVE, /* Native - OC6# pin */ - .gpio11 = GPIO_MODE_NATIVE, /* Native - SMBALERT# pin */ - .gpio12 = GPIO_MODE_NATIVE, /* Native - LAN_PHY_PWR_CTRL */ - .gpio13 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio14 = GPIO_MODE_NATIVE, /* Native - OC7# pin */ - .gpio15 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio16 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio17 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin */ - .gpio19 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio20 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio21 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio22 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio23 = GPIO_MODE_NATIVE, /* Native - LDRQ1# pin */ - .gpio24 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio25 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio26 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ4# pin */ - .gpio27 = GPIO_MODE_GPIO, /* Unknown Input */ /* Vendor supplied DSDT sets this conditionally - when going to suspend (S3, S4, S5). */ - .gpio28 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio29 = GPIO_MODE_NATIVE, /* Native - SLP_LAN# pin, forced by soft strap */ - .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# pin */ - .gpio31 = GPIO_MODE_NATIVE /* Native - ACPRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio1 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio2 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio3 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio4 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio5 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio6 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio7 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio8 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio9 = GPIO_DIR_INPUT, /* Native */ - .gpio10 = GPIO_DIR_INPUT, /* Native */ - .gpio11 = GPIO_DIR_INPUT, /* Native */ - .gpio12 = GPIO_DIR_INPUT, /* Native */ - .gpio13 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio14 = GPIO_DIR_INPUT, /* Native */ - .gpio15 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio16 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio17 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio18 = GPIO_DIR_INPUT, /* Native */ - .gpio19 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio20 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio21 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio22 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio23 = GPIO_DIR_INPUT, /* Native */ - .gpio24 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio25 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio26 = GPIO_DIR_INPUT, /* Native */ - .gpio27 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio28 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio29 = GPIO_DIR_INPUT, /* Native */ - .gpio30 = GPIO_DIR_INPUT, /* Native */ - .gpio31 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio1 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio2 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio3 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio4 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio5 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio6 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio7 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio8 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio9 = GPIO_LEVEL_LOW, /* Native */ - .gpio10 = GPIO_LEVEL_LOW, /* Native */ - .gpio11 = GPIO_LEVEL_LOW, /* Native */ - .gpio12 = GPIO_LEVEL_LOW, /* Native */ - .gpio13 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio14 = GPIO_LEVEL_LOW, /* Native */ - .gpio15 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio16 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio17 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio18 = GPIO_LEVEL_LOW, /* Native */ - .gpio19 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio20 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio21 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio22 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio23 = GPIO_LEVEL_LOW, /* Native */ - .gpio24 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio25 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio26 = GPIO_LEVEL_LOW, /* Native */ - .gpio27 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio28 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio29 = GPIO_LEVEL_LOW, /* Native */ - .gpio30 = GPIO_LEVEL_LOW, /* Native */ - .gpio31 = GPIO_LEVEL_LOW, /* Native */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* Native - CLKRUN# pin */ - .gpio33 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio34 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio35 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio36 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio37 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio38 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio39 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio40 = GPIO_MODE_NATIVE, /* Native - OC1# pin */ - .gpio41 = GPIO_MODE_NATIVE, /* Native - OC2# pin */ - .gpio42 = GPIO_MODE_NATIVE, /* Native - OC3# pin */ - .gpio43 = GPIO_MODE_NATIVE, /* Native - OC4# pin */ - .gpio44 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ5# pin */ - .gpio45 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ6# pin */ - .gpio46 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ7# pin */ - .gpio47 = GPIO_MODE_NATIVE, /* Native - PEG_A_CLKRQ# pin */ - .gpio48 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio49 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio50 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio51 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio52 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio53 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio54 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio55 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio56 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio57 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio58 = GPIO_MODE_NATIVE, /* Native - SML1CLK */ - .gpio59 = GPIO_MODE_NATIVE, /* Native - OC0# pin */ - .gpio60 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio61 = GPIO_MODE_NATIVE, /* Native - SUS_STAT# pin*/ - .gpio62 = GPIO_MODE_NATIVE, /* Native - SUSCLK */ - .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5# */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, /* Native */ - .gpio33 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio34 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio35 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio36 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio37 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio38 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio39 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio40 = GPIO_DIR_INPUT, /* Native */ - .gpio41 = GPIO_DIR_INPUT, /* Native */ - .gpio42 = GPIO_DIR_INPUT, /* Native */ - .gpio43 = GPIO_DIR_INPUT, /* Native */ - .gpio44 = GPIO_DIR_INPUT, /* Native */ - .gpio45 = GPIO_DIR_INPUT, /* Native */ - .gpio46 = GPIO_DIR_INPUT, /* Native */ - .gpio47 = GPIO_DIR_INPUT, /* Native */ - .gpio48 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio49 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio50 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio51 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio52 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio53 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio54 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio55 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio56 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio57 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio58 = GPIO_DIR_INPUT, /* Native */ - .gpio59 = GPIO_DIR_INPUT, /* Native */ - .gpio60 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio61 = GPIO_DIR_INPUT, /* Native */ - .gpio62 = GPIO_DIR_INPUT, /* Native */ - .gpio63 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, /* Native */ - .gpio33 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio34 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio35 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio36 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio37 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio38 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio39 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio40 = GPIO_LEVEL_LOW, /* Native */ - .gpio41 = GPIO_LEVEL_LOW, /* Native */ - .gpio42 = GPIO_LEVEL_LOW, /* Native */ - .gpio43 = GPIO_LEVEL_LOW, /* Native */ - .gpio44 = GPIO_LEVEL_LOW, /* Native */ - .gpio45 = GPIO_LEVEL_LOW, /* Native */ - .gpio46 = GPIO_LEVEL_LOW, /* Native */ - .gpio47 = GPIO_LEVEL_LOW, /* Native */ - .gpio48 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio49 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio50 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio51 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio52 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio53 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio54 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio55 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio56 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio57 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio58 = GPIO_LEVEL_LOW, /* Native */ - .gpio59 = GPIO_LEVEL_LOW, /* Native */ - .gpio60 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio61 = GPIO_LEVEL_LOW, /* Native */ - .gpio62 = GPIO_LEVEL_LOW, /* Native */ - .gpio63 = GPIO_LEVEL_LOW, /* Native */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio65 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio66 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio67 = GPIO_MODE_NATIVE, /* Native - CLKOUTFLEX3 */ - .gpio68 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio69 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio70 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio71 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio72 = GPIO_MODE_NATIVE, /* Native - nothing on mobile */ - .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# pin */ - .gpio74 = GPIO_MODE_NATIVE, /* Native - SML1ALERT#/PCHHOT# pin */ - .gpio75 = GPIO_MODE_NATIVE, /* Native - SML1DATA */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio65 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio67 = GPIO_DIR_INPUT, /* Native */ - .gpio68 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio69 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio70 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio71 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio72 = GPIO_DIR_INPUT, /* Native */ - .gpio73 = GPIO_DIR_INPUT, /* Native */ - .gpio74 = GPIO_DIR_INPUT, /* Native */ - .gpio75 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio65 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio66 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio67 = GPIO_LEVEL_LOW, /* Native */ - .gpio68 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio69 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio70 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio71 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio72 = GPIO_LEVEL_LOW, /* Native */ - .gpio73 = GPIO_LEVEL_LOW, /* Native */ - .gpio74 = GPIO_LEVEL_LOW, /* Native */ - .gpio75 = GPIO_LEVEL_LOW, /* Native */ -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 197b460..8f3f900 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -29,11 +29,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h"
void pch_enable_lpc(void) { diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index d83f26d..26526c9 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -27,3 +27,4 @@ $(SPD_BIN): cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := spd +romstage-y += gpio.c diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c new file mode 100644 index 0000000..e5737bb --- /dev/null +++ b/src/mainboard/samsung/lumpy/gpio.c @@ -0,0 +1,332 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LUMPY_GPIO_H +#define LUMPY_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +/* + * GPIO SET 1 includes GPIO0 to GPIO31 + */ + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ + .gpio1 = GPIO_MODE_GPIO, /* KBC3_EXTSMI# */ + .gpio2 = GPIO_MODE_NATIVE, /* CHP3_ALSINT# (Light Sensor) */ + .gpio3 = GPIO_MODE_NATIVE, /* CHP3_TP_INT# (Trackpad) */ + .gpio4 = GPIO_MODE_NONE, + .gpio5 = GPIO_MODE_GPIO, /* SIM3_CARD_DET# */ + .gpio6 = GPIO_MODE_NONE, + .gpio7 = GPIO_MODE_GPIO, /* KBC3_RUNSCI# */ + .gpio8 = GPIO_MODE_GPIO, /* CHP3_INTELBT_OFF# */ + .gpio9 = GPIO_MODE_NONE, + .gpio10 = GPIO_MODE_NONE, + .gpio11 = GPIO_MODE_GPIO, /* CHP3_TP_INT# (Trackpad wake) */ + .gpio12 = GPIO_MODE_NONE, + .gpio13 = GPIO_MODE_GPIO, /* CHP3_DEBUG13 */ + .gpio14 = GPIO_MODE_GPIO, /* KBC3_WAKESCI# */ + .gpio15 = GPIO_MODE_NONE, + .gpio16 = GPIO_MODE_NONE, + .gpio17 = GPIO_MODE_GPIO, /* KBC3_DVP_MODE */ + .gpio18 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ1# */ + .gpio19 = GPIO_MODE_NONE, + .gpio20 = GPIO_MODE_NONE, + .gpio21 = GPIO_MODE_GPIO, /* LCD3_SIZE */ + .gpio22 = GPIO_MODE_GPIO, /* CHP3_BIOS_CRISIS# */ + .gpio23 = GPIO_MODE_NONE, + .gpio24 = GPIO_MODE_GPIO, /* KBC3_SPI_WP# */ + .gpio25 = GPIO_MODE_NONE, + .gpio26 = GPIO_MODE_NATIVE, /* LAN3_CLKREQ# */ + .gpio27 = GPIO_MODE_NONE, + .gpio28 = GPIO_MODE_NONE, + .gpio29 = GPIO_MODE_NONE, + .gpio30 = GPIO_MODE_NATIVE, /* CHP3_SUSWARN# */ + .gpio31 = GPIO_MODE_NATIVE, /* KBC3_AC_PRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_LOW, + .gpio30 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_NO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_NO_INVERT, +}; + +/* + * GPIO SET 2 includes GPIO32 to GPIO63 + */ + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ + .gpio33 = GPIO_MODE_GPIO, /* Onboard Memory Capacity */ + .gpio34 = GPIO_MODE_NONE, + .gpio35 = GPIO_MODE_GPIO, /* CHP3_WLAN_OFF# */ + .gpio36 = GPIO_MODE_NONE, + .gpio37 = GPIO_MODE_GPIO, /* CHP3_FDI_OVRVLTG */ + .gpio38 = GPIO_MODE_GPIO, /* CHP3_3G_OFF# */ + .gpio39 = GPIO_MODE_NONE, + .gpio40 = GPIO_MODE_NATIVE, /* USB3_OC1# */ + .gpio41 = GPIO_MODE_GPIO, /* Onboard Memory Revision */ + .gpio42 = GPIO_MODE_GPIO, /* CHP3_REC_MODE# */ + .gpio43 = GPIO_MODE_GPIO, /* CHP3_HSPA_PWRON# */ + .gpio44 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL2# */ + .gpio45 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL3# */ + .gpio46 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG1_CTL2# */ + .gpio47 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE0 */ + .gpio48 = GPIO_MODE_GPIO, /* CHP3_BT_OFF# */ + .gpio49 = GPIO_MODE_GPIO, /* Onboard Memory Vendor */ + .gpio50 = GPIO_MODE_NONE, + .gpio51 = GPIO_MODE_NONE, + .gpio52 = GPIO_MODE_NONE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NONE, + .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR */ + .gpio56 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE1 */ + .gpio57 = GPIO_MODE_GPIO, /* CHP3_DEBUG10 */ + .gpio58 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMCLK# */ + .gpio59 = GPIO_MODE_NATIVE, /* USB3_OC0# */ + .gpio60 = GPIO_MODE_GPIO, /* CHP3_DRAMRST_GATE */ + .gpio61 = GPIO_MODE_NATIVE, /* CHP3_SUSSTAT# */ + .gpio62 = GPIO_MODE_NATIVE, /* CHP3_SUSCLK */ + .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio47 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, /* Enable WLAN */ + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, /* Enable 3G */ + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB0 SDP */ + .gpio45 = GPIO_LEVEL_LOW, /* CTL3=0 for USB0 SDP */ + .gpio46 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB1 SDP */ + .gpio47 = GPIO_LEVEL_HIGH, /* Enable USB0 */ + .gpio48 = GPIO_LEVEL_LOW, /* Disable Bluetooth */ + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, /* Enable USB1 */ + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_LOW, + .gpio59 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +/* + * GPIO SET 3 includes GPIO64 to GPIO75 + */ + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NONE, + .gpio65 = GPIO_MODE_NONE, + .gpio66 = GPIO_MODE_NONE, + .gpio67 = GPIO_MODE_NONE, + .gpio68 = GPIO_MODE_NONE, + .gpio69 = GPIO_MODE_GPIO, /* PEX3_WWAN_DET# */ + .gpio70 = GPIO_MODE_GPIO, /* CHP3_WLAN_RST# */ + .gpio71 = GPIO_MODE_GPIO, /* CHP3_WLAN_PWRON */ + .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# (pullup) */ + .gpio73 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG1_CTL3# */ + .gpio74 = GPIO_MODE_NONE, + .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, /* WLAN out of reset */ + .gpio71 = GPIO_LEVEL_HIGH, /* WLAN power on */ + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_LOW, /* USB1 CTL3=0 for SDP */ + .gpio74 = GPIO_LEVEL_LOW, + .gpio75 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio38 = GPIO_RESET_RSMRST, + .gpio43 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif diff --git a/src/mainboard/samsung/lumpy/gpio.h b/src/mainboard/samsung/lumpy/gpio.h deleted file mode 100644 index e5737bb..0000000 --- a/src/mainboard/samsung/lumpy/gpio.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LUMPY_GPIO_H -#define LUMPY_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -/* - * GPIO SET 1 includes GPIO0 to GPIO31 - */ - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ - .gpio1 = GPIO_MODE_GPIO, /* KBC3_EXTSMI# */ - .gpio2 = GPIO_MODE_NATIVE, /* CHP3_ALSINT# (Light Sensor) */ - .gpio3 = GPIO_MODE_NATIVE, /* CHP3_TP_INT# (Trackpad) */ - .gpio4 = GPIO_MODE_NONE, - .gpio5 = GPIO_MODE_GPIO, /* SIM3_CARD_DET# */ - .gpio6 = GPIO_MODE_NONE, - .gpio7 = GPIO_MODE_GPIO, /* KBC3_RUNSCI# */ - .gpio8 = GPIO_MODE_GPIO, /* CHP3_INTELBT_OFF# */ - .gpio9 = GPIO_MODE_NONE, - .gpio10 = GPIO_MODE_NONE, - .gpio11 = GPIO_MODE_GPIO, /* CHP3_TP_INT# (Trackpad wake) */ - .gpio12 = GPIO_MODE_NONE, - .gpio13 = GPIO_MODE_GPIO, /* CHP3_DEBUG13 */ - .gpio14 = GPIO_MODE_GPIO, /* KBC3_WAKESCI# */ - .gpio15 = GPIO_MODE_NONE, - .gpio16 = GPIO_MODE_NONE, - .gpio17 = GPIO_MODE_GPIO, /* KBC3_DVP_MODE */ - .gpio18 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ1# */ - .gpio19 = GPIO_MODE_NONE, - .gpio20 = GPIO_MODE_NONE, - .gpio21 = GPIO_MODE_GPIO, /* LCD3_SIZE */ - .gpio22 = GPIO_MODE_GPIO, /* CHP3_BIOS_CRISIS# */ - .gpio23 = GPIO_MODE_NONE, - .gpio24 = GPIO_MODE_GPIO, /* KBC3_SPI_WP# */ - .gpio25 = GPIO_MODE_NONE, - .gpio26 = GPIO_MODE_NATIVE, /* LAN3_CLKREQ# */ - .gpio27 = GPIO_MODE_NONE, - .gpio28 = GPIO_MODE_NONE, - .gpio29 = GPIO_MODE_NONE, - .gpio30 = GPIO_MODE_NATIVE, /* CHP3_SUSWARN# */ - .gpio31 = GPIO_MODE_NATIVE, /* KBC3_AC_PRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_OUTPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_OUTPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_INPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_INPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_LOW, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_LOW, - .gpio8 = GPIO_LEVEL_LOW, - .gpio9 = GPIO_LEVEL_LOW, - .gpio10 = GPIO_LEVEL_LOW, - .gpio11 = GPIO_LEVEL_LOW, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - .gpio14 = GPIO_LEVEL_LOW, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_LOW, - .gpio19 = GPIO_LEVEL_LOW, - .gpio20 = GPIO_LEVEL_LOW, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_LOW, - .gpio26 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_LOW, - .gpio30 = GPIO_LEVEL_LOW, - .gpio31 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio0 = GPIO_NO_INVERT, - .gpio1 = GPIO_INVERT, - .gpio2 = GPIO_INVERT, - .gpio3 = GPIO_INVERT, - .gpio4 = GPIO_NO_INVERT, - .gpio5 = GPIO_INVERT, - .gpio6 = GPIO_NO_INVERT, - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_NO_INVERT, - .gpio9 = GPIO_NO_INVERT, - .gpio10 = GPIO_NO_INVERT, - .gpio11 = GPIO_INVERT, - .gpio12 = GPIO_NO_INVERT, - .gpio13 = GPIO_NO_INVERT, - .gpio14 = GPIO_INVERT, - .gpio15 = GPIO_NO_INVERT, -}; - -/* - * GPIO SET 2 includes GPIO32 to GPIO63 - */ - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ - .gpio33 = GPIO_MODE_GPIO, /* Onboard Memory Capacity */ - .gpio34 = GPIO_MODE_NONE, - .gpio35 = GPIO_MODE_GPIO, /* CHP3_WLAN_OFF# */ - .gpio36 = GPIO_MODE_NONE, - .gpio37 = GPIO_MODE_GPIO, /* CHP3_FDI_OVRVLTG */ - .gpio38 = GPIO_MODE_GPIO, /* CHP3_3G_OFF# */ - .gpio39 = GPIO_MODE_NONE, - .gpio40 = GPIO_MODE_NATIVE, /* USB3_OC1# */ - .gpio41 = GPIO_MODE_GPIO, /* Onboard Memory Revision */ - .gpio42 = GPIO_MODE_GPIO, /* CHP3_REC_MODE# */ - .gpio43 = GPIO_MODE_GPIO, /* CHP3_HSPA_PWRON# */ - .gpio44 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL2# */ - .gpio45 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL3# */ - .gpio46 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG1_CTL2# */ - .gpio47 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE0 */ - .gpio48 = GPIO_MODE_GPIO, /* CHP3_BT_OFF# */ - .gpio49 = GPIO_MODE_GPIO, /* Onboard Memory Vendor */ - .gpio50 = GPIO_MODE_NONE, - .gpio51 = GPIO_MODE_NONE, - .gpio52 = GPIO_MODE_NONE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NONE, - .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR */ - .gpio56 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE1 */ - .gpio57 = GPIO_MODE_GPIO, /* CHP3_DEBUG10 */ - .gpio58 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMCLK# */ - .gpio59 = GPIO_MODE_NATIVE, /* USB3_OC0# */ - .gpio60 = GPIO_MODE_GPIO, /* CHP3_DRAMRST_GATE */ - .gpio61 = GPIO_MODE_NATIVE, /* CHP3_SUSSTAT# */ - .gpio62 = GPIO_MODE_NATIVE, /* CHP3_SUSCLK */ - .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_OUTPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_OUTPUT, - .gpio44 = GPIO_DIR_OUTPUT, - .gpio45 = GPIO_DIR_OUTPUT, - .gpio46 = GPIO_DIR_OUTPUT, - .gpio47 = GPIO_DIR_OUTPUT, - .gpio48 = GPIO_DIR_OUTPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_INPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_INPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_INPUT, - .gpio56 = GPIO_DIR_OUTPUT, - .gpio57 = GPIO_DIR_OUTPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_INPUT, - .gpio62 = GPIO_DIR_INPUT, - .gpio63 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_HIGH, /* Enable WLAN */ - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_HIGH, /* Enable 3G */ - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_LOW, - .gpio41 = GPIO_LEVEL_LOW, - .gpio42 = GPIO_LEVEL_LOW, - .gpio43 = GPIO_LEVEL_LOW, - .gpio44 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB0 SDP */ - .gpio45 = GPIO_LEVEL_LOW, /* CTL3=0 for USB0 SDP */ - .gpio46 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB1 SDP */ - .gpio47 = GPIO_LEVEL_HIGH, /* Enable USB0 */ - .gpio48 = GPIO_LEVEL_LOW, /* Disable Bluetooth */ - .gpio49 = GPIO_LEVEL_LOW, - .gpio50 = GPIO_LEVEL_LOW, - .gpio51 = GPIO_LEVEL_LOW, - .gpio52 = GPIO_LEVEL_LOW, - .gpio53 = GPIO_LEVEL_LOW, - .gpio54 = GPIO_LEVEL_LOW, - .gpio55 = GPIO_LEVEL_LOW, - .gpio56 = GPIO_LEVEL_HIGH, /* Enable USB1 */ - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_LOW, - .gpio59 = GPIO_LEVEL_LOW, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, -}; - -/* - * GPIO SET 3 includes GPIO64 to GPIO75 - */ - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NONE, - .gpio65 = GPIO_MODE_NONE, - .gpio66 = GPIO_MODE_NONE, - .gpio67 = GPIO_MODE_NONE, - .gpio68 = GPIO_MODE_NONE, - .gpio69 = GPIO_MODE_GPIO, /* PEX3_WWAN_DET# */ - .gpio70 = GPIO_MODE_GPIO, /* CHP3_WLAN_RST# */ - .gpio71 = GPIO_MODE_GPIO, /* CHP3_WLAN_PWRON */ - .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# (pullup) */ - .gpio73 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG1_CTL3# */ - .gpio74 = GPIO_MODE_NONE, - .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, - .gpio65 = GPIO_DIR_INPUT, - .gpio66 = GPIO_DIR_INPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_OUTPUT, - .gpio71 = GPIO_DIR_OUTPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio73 = GPIO_DIR_OUTPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_LOW, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_HIGH, /* WLAN out of reset */ - .gpio71 = GPIO_LEVEL_HIGH, /* WLAN power on */ - .gpio72 = GPIO_LEVEL_LOW, - .gpio73 = GPIO_LEVEL_LOW, /* USB1 CTL3=0 for SDP */ - .gpio74 = GPIO_LEVEL_LOW, - .gpio75 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set2 pch_gpio_set2_reset = { - .gpio38 = GPIO_RESET_RSMRST, - .gpio43 = GPIO_RESET_RSMRST, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - .reset = &pch_gpio_set2_reset, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; - -#endif diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index b91573b..791afe9 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -32,12 +32,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> #include "option_table.h" -#include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index c29b1001..b3bf53f 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -15,3 +15,4 @@
romstage-y += chromeos.c ramstage-y += chromeos.c +romstage-y += gpio.c diff --git a/src/mainboard/samsung/stumpy/gpio.c b/src/mainboard/samsung/stumpy/gpio.c new file mode 100644 index 0000000..1371155 --- /dev/null +++ b/src/mainboard/samsung/stumpy/gpio.c @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STUMPY_GPIO_H +#define STUMPY_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +/* + * GPIO SET 1 includes GPIO0 to GPIO31 + */ + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ + .gpio1 = GPIO_MODE_GPIO, /* SIO3_EXTSMI# */ + .gpio2 = GPIO_MODE_NONE, + .gpio3 = GPIO_MODE_NONE, + .gpio4 = GPIO_MODE_NONE, + .gpio5 = GPIO_MODE_NONE, + .gpio6 = GPIO_MODE_NONE, + .gpio7 = GPIO_MODE_NONE, + .gpio8 = GPIO_MODE_GPIO, /* CHP3_INTELBT_OFF# */ + .gpio9 = GPIO_MODE_NATIVE, /* USB_OC13# */ + .gpio10 = GPIO_MODE_NATIVE, /* USB_OC12# */ + .gpio11 = GPIO_MODE_NONE, + .gpio12 = GPIO_MODE_NONE, + .gpio13 = GPIO_MODE_GPIO, /* CHP3_DEBUG13 */ + .gpio14 = GPIO_MODE_GPIO, /* SIO3_WAKESCI# */ + .gpio15 = GPIO_MODE_NONE, + .gpio16 = GPIO_MODE_NONE, + .gpio17 = GPIO_MODE_GPIO, /* KBC3_DVP_MODE */ + .gpio18 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ1# */ + .gpio19 = GPIO_MODE_NONE, + .gpio20 = GPIO_MODE_NONE, + .gpio21 = GPIO_MODE_NONE, + .gpio22 = GPIO_MODE_GPIO, /* CHP3_BIOS_CRISIS# */ + .gpio23 = GPIO_MODE_NONE, + .gpio24 = GPIO_MODE_NONE, + .gpio25 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ3# */ + .gpio26 = GPIO_MODE_NATIVE, /* LAN3_CLKREQ# */ + .gpio27 = GPIO_MODE_NONE, + .gpio28 = GPIO_MODE_NONE, + .gpio29 = GPIO_MODE_NONE, + .gpio30 = GPIO_MODE_NATIVE, /* CHP3_SUSWARN# */ + .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT (pullup) */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_LOW, + .gpio30 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_LOW, +}; + +/* + * GPIO SET 2 includes GPIO32 to GPIO63 + */ + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ + .gpio33 = GPIO_MODE_NONE, + .gpio34 = GPIO_MODE_NONE, + .gpio35 = GPIO_MODE_GPIO, /* CHP3_WLAN_OFF# */ + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, /* CHP3_FDI_OVRVLTG */ + .gpio38 = GPIO_MODE_NONE, + .gpio39 = GPIO_MODE_NONE, + .gpio40 = GPIO_MODE_NATIVE, /* USB3_OC1# */ + .gpio41 = GPIO_MODE_NATIVE, /* USB3_OC4# */ + .gpio42 = GPIO_MODE_GPIO, /* CHP3_REC_MODE# */ + .gpio43 = GPIO_MODE_NATIVE, /* USB3_OC8# */ + .gpio44 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL2# */ + .gpio45 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL3# */ + .gpio46 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG4_CTL2# */ + .gpio47 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE0 */ + .gpio48 = GPIO_MODE_GPIO, /* CHP3_BT_OFF# */ + .gpio49 = GPIO_MODE_NONE, + .gpio50 = GPIO_MODE_NONE, + .gpio51 = GPIO_MODE_NONE, + .gpio52 = GPIO_MODE_NONE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NONE, + .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR */ + .gpio56 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE4 */ + .gpio57 = GPIO_MODE_GPIO, /* CHP3_DEBUG10 */ + .gpio58 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMCLK# */ + .gpio59 = GPIO_MODE_NATIVE, /* USB3_OC0# */ + .gpio60 = GPIO_MODE_GPIO, /* CHP3_DRAMRST_GATE */ + .gpio61 = GPIO_MODE_NONE, + .gpio62 = GPIO_MODE_NATIVE, /* CHP3_SUSCLK */ + .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio47 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_LOW, + .gpio59 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +/* + * GPIO SET 3 includes GPIO64 to GPIO75 + */ + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, /* CLK3_SIO48 */ + .gpio65 = GPIO_MODE_NONE, + .gpio66 = GPIO_MODE_NONE, + .gpio67 = GPIO_MODE_NONE, + .gpio68 = GPIO_MODE_GPIO, /* CHP3_SPI_WP */ + .gpio69 = GPIO_MODE_NONE, + .gpio70 = GPIO_MODE_NONE, + .gpio71 = GPIO_MODE_NONE, + .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# (pullup) */ + .gpio73 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG4_CTL3# */ + .gpio74 = GPIO_MODE_NONE, + .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_LOW, + .gpio75 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif diff --git a/src/mainboard/samsung/stumpy/gpio.h b/src/mainboard/samsung/stumpy/gpio.h deleted file mode 100644 index 1371155..0000000 --- a/src/mainboard/samsung/stumpy/gpio.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef STUMPY_GPIO_H -#define STUMPY_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -/* - * GPIO SET 1 includes GPIO0 to GPIO31 - */ - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ - .gpio1 = GPIO_MODE_GPIO, /* SIO3_EXTSMI# */ - .gpio2 = GPIO_MODE_NONE, - .gpio3 = GPIO_MODE_NONE, - .gpio4 = GPIO_MODE_NONE, - .gpio5 = GPIO_MODE_NONE, - .gpio6 = GPIO_MODE_NONE, - .gpio7 = GPIO_MODE_NONE, - .gpio8 = GPIO_MODE_GPIO, /* CHP3_INTELBT_OFF# */ - .gpio9 = GPIO_MODE_NATIVE, /* USB_OC13# */ - .gpio10 = GPIO_MODE_NATIVE, /* USB_OC12# */ - .gpio11 = GPIO_MODE_NONE, - .gpio12 = GPIO_MODE_NONE, - .gpio13 = GPIO_MODE_GPIO, /* CHP3_DEBUG13 */ - .gpio14 = GPIO_MODE_GPIO, /* SIO3_WAKESCI# */ - .gpio15 = GPIO_MODE_NONE, - .gpio16 = GPIO_MODE_NONE, - .gpio17 = GPIO_MODE_GPIO, /* KBC3_DVP_MODE */ - .gpio18 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ1# */ - .gpio19 = GPIO_MODE_NONE, - .gpio20 = GPIO_MODE_NONE, - .gpio21 = GPIO_MODE_NONE, - .gpio22 = GPIO_MODE_GPIO, /* CHP3_BIOS_CRISIS# */ - .gpio23 = GPIO_MODE_NONE, - .gpio24 = GPIO_MODE_NONE, - .gpio25 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ3# */ - .gpio26 = GPIO_MODE_NATIVE, /* LAN3_CLKREQ# */ - .gpio27 = GPIO_MODE_NONE, - .gpio28 = GPIO_MODE_NONE, - .gpio29 = GPIO_MODE_NONE, - .gpio30 = GPIO_MODE_NATIVE, /* CHP3_SUSWARN# */ - .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT (pullup) */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_OUTPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_OUTPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_INPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_INPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_LOW, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_LOW, - .gpio8 = GPIO_LEVEL_HIGH, - .gpio9 = GPIO_LEVEL_LOW, - .gpio10 = GPIO_LEVEL_LOW, - .gpio11 = GPIO_LEVEL_LOW, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - .gpio14 = GPIO_LEVEL_LOW, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_LOW, - .gpio19 = GPIO_LEVEL_LOW, - .gpio20 = GPIO_LEVEL_LOW, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_LOW, - .gpio26 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_LOW, - .gpio30 = GPIO_LEVEL_LOW, - .gpio31 = GPIO_LEVEL_LOW, -}; - -/* - * GPIO SET 2 includes GPIO32 to GPIO63 - */ - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ - .gpio33 = GPIO_MODE_NONE, - .gpio34 = GPIO_MODE_NONE, - .gpio35 = GPIO_MODE_GPIO, /* CHP3_WLAN_OFF# */ - .gpio36 = GPIO_MODE_GPIO, - .gpio37 = GPIO_MODE_GPIO, /* CHP3_FDI_OVRVLTG */ - .gpio38 = GPIO_MODE_NONE, - .gpio39 = GPIO_MODE_NONE, - .gpio40 = GPIO_MODE_NATIVE, /* USB3_OC1# */ - .gpio41 = GPIO_MODE_NATIVE, /* USB3_OC4# */ - .gpio42 = GPIO_MODE_GPIO, /* CHP3_REC_MODE# */ - .gpio43 = GPIO_MODE_NATIVE, /* USB3_OC8# */ - .gpio44 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL2# */ - .gpio45 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL3# */ - .gpio46 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG4_CTL2# */ - .gpio47 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE0 */ - .gpio48 = GPIO_MODE_GPIO, /* CHP3_BT_OFF# */ - .gpio49 = GPIO_MODE_NONE, - .gpio50 = GPIO_MODE_NONE, - .gpio51 = GPIO_MODE_NONE, - .gpio52 = GPIO_MODE_NONE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NONE, - .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR */ - .gpio56 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE4 */ - .gpio57 = GPIO_MODE_GPIO, /* CHP3_DEBUG10 */ - .gpio58 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMCLK# */ - .gpio59 = GPIO_MODE_NATIVE, /* USB3_OC0# */ - .gpio60 = GPIO_MODE_GPIO, /* CHP3_DRAMRST_GATE */ - .gpio61 = GPIO_MODE_NONE, - .gpio62 = GPIO_MODE_NATIVE, /* CHP3_SUSCLK */ - .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_OUTPUT, - .gpio45 = GPIO_DIR_OUTPUT, - .gpio46 = GPIO_DIR_OUTPUT, - .gpio47 = GPIO_DIR_OUTPUT, - .gpio48 = GPIO_DIR_OUTPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_INPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_INPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_INPUT, - .gpio56 = GPIO_DIR_OUTPUT, - .gpio57 = GPIO_DIR_OUTPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_INPUT, - .gpio62 = GPIO_DIR_INPUT, - .gpio63 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_HIGH, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_LOW, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_LOW, - .gpio41 = GPIO_LEVEL_LOW, - .gpio42 = GPIO_LEVEL_LOW, - .gpio43 = GPIO_LEVEL_LOW, - .gpio44 = GPIO_LEVEL_HIGH, - .gpio45 = GPIO_LEVEL_LOW, - .gpio46 = GPIO_LEVEL_HIGH, - .gpio47 = GPIO_LEVEL_HIGH, - .gpio48 = GPIO_LEVEL_HIGH, - .gpio49 = GPIO_LEVEL_LOW, - .gpio50 = GPIO_LEVEL_LOW, - .gpio51 = GPIO_LEVEL_LOW, - .gpio52 = GPIO_LEVEL_LOW, - .gpio53 = GPIO_LEVEL_LOW, - .gpio54 = GPIO_LEVEL_LOW, - .gpio55 = GPIO_LEVEL_LOW, - .gpio56 = GPIO_LEVEL_HIGH, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_LOW, - .gpio59 = GPIO_LEVEL_LOW, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, -}; - -/* - * GPIO SET 3 includes GPIO64 to GPIO75 - */ - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NATIVE, /* CLK3_SIO48 */ - .gpio65 = GPIO_MODE_NONE, - .gpio66 = GPIO_MODE_NONE, - .gpio67 = GPIO_MODE_NONE, - .gpio68 = GPIO_MODE_GPIO, /* CHP3_SPI_WP */ - .gpio69 = GPIO_MODE_NONE, - .gpio70 = GPIO_MODE_NONE, - .gpio71 = GPIO_MODE_NONE, - .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# (pullup) */ - .gpio73 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG4_CTL3# */ - .gpio74 = GPIO_MODE_NONE, - .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, - .gpio65 = GPIO_DIR_INPUT, - .gpio66 = GPIO_DIR_INPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_INPUT, - .gpio71 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio73 = GPIO_DIR_OUTPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_LOW, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_LOW, - .gpio71 = GPIO_LEVEL_LOW, - .gpio72 = GPIO_LEVEL_LOW, - .gpio73 = GPIO_LEVEL_LOW, - .gpio74 = GPIO_LEVEL_LOW, - .gpio75 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; - -#endif diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 2caf23e..87528af 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -32,12 +32,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> #include <tpm.h> -#include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif