Marx Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54079 )
Change subject: soc/intel/cannonlake: Provide RefreshWm for users to config ......................................................................
soc/intel/cannonlake: Provide RefreshWm for users to config
To mitigate Row Hammer vulnerability, we could set refresh water mark to low (0).
branch=master BUG=none TEST=add RefreshWm=0 in devicetree and check if 0xfed14238 bits[15:8] are changed.
Signed-off-by: Marx Wang marx.wang@intel.com Change-Id: Ic364df8b446f291f410e09825075f5b5251621ff --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/54079/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3c8a68b..e1e98dd 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -435,6 +435,14 @@
/* Disable CPU Turbo in IA32_MISC_ENABLE */ bool cpu_turbo_disable; + + /* + * Refresh watermark value: + * 1 : Default value in FSP, high refresh watermark. + * 0 : low watermark to mitigate Row Hammer vulnerability. + * + */ + uint8_t RefreshWm; };
typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 2bb3024..3779cc7 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -151,6 +151,9 @@ /* Set HECI1 PCI BAR address */ m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;
+ /* Set refresh watermark */ + m_cfg->RefreshWm = config->RefreshWm; + mainboard_memory_init_params(mupd); }