Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82113?usp=email )
Change subject: soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable ......................................................................
soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable
As described in Intel document 336464 (8th gen S series datasheet volume 1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2 lanes. This lets mainboards provide a VGA output without sacrificing one of the main 4-lane DDIs. Newer platforms seem to be lacking this.
However, the way this is structured in coreboot does not allow boards to choose whether bifurcation should be enabled. Most boards in the tree do not use DDI-E (it doesn't exist on mobile platforms), but there are some boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to provide a VGA output.
Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to specify whether a platform supports DDI-A bifurcation at all (do nothing otherwise, maintaining the original code's behaviour). If bifurcation is supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register.
Change-Id: I516538db77509209d371f3f49c920476e06b052f Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/graphics/Kconfig M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/skylake/Kconfig 4 files changed, 31 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7548e46..3aa06f4 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -64,7 +64,7 @@ select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index b5776b0..eaa429e 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -8,10 +8,20 @@
if SOC_INTEL_COMMON_BLOCK_GRAPHICS
-config SOC_INTEL_CONFIGURE_DDI_A_4_LANES +config SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION bool help - Selected by platforms that require DDI-A bifurcation setup. + Skylake, Kaby Lake and Coffee Lake desktop CPUs support eDP + bifurcation, i.e. 4 eDP lanes get split between DDI-A (eDP) + and DDI-E (DP, used for VGA). Selected from SoC Kconfig, if + applicable. + +config SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION + bool + depends on SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION + help + Selected by mainboards that use DDI-E, which is most commonly + used to drive a DP-to-VGA adapter to provide a VGA connector.
config SOC_INTEL_DISABLE_IGD bool "Disable Integrated GFX Controller (0:2:0)" diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index c38b30f..1a0d64d 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -124,6 +124,21 @@ return graphics_get_framebuffer_address() && get_external_display_status(); }
+static void configure_ddi_a_bifurcation(void) +{ + u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); + /* Only program if the buffer is not enabled yet. */ + if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) + return; + + if (CONFIG(SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION)) + ddi_buf_ctl &= ~DDI_A_4_LANES; + else + ddi_buf_ctl |= DDI_A_4_LANES; + + graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); +} + static void gma_init(struct device *const dev) { intel_gma_init_igd_opregion(); @@ -135,12 +150,8 @@ if (!CONFIG(RUN_FSP_GOP)) graphics_soc_panel_init(dev);
- if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) { - const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - /* Only program if the buffer is not enabled yet. */ - if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES); - } + if (CONFIG(SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION) && !acpi_is_wakeup_s3()) + configure_ddi_a_bifurcation();
/* * GFX PEIM module inside FSP binary is taking care of graphics diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0d38804..3ec84ab 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -62,7 +62,7 @@ select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER