Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
The value for that macro should be 1<<19. This is confirmed by the Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE. See Intel Atom® Processor C3000 Product Family Datasheet (February 2018) : https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-seri...
Signed-off-by: Patrick Havelange patrick.havelange@essensium.com Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33573 Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: David Guckian Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/denverton_ns/include/soc/gpio_defs.h 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve HAOUAS Elyes: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h index 43e0647..ae61e6d 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h @@ -182,7 +182,7 @@ #define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01
// GPIO Input Route SCI -#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 10) +#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 19) #define N_PCH_GPIO_RX_SCI_ROUTE 19 #define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 #define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01