Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32284 )
Change subject: mediatek/mt8183: fix mode register setting fail issue ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32284/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32284/1//COMMIT_MSG@9 PS1, Line 9: the mode register setting of DRAM maybe failed without delay operate, : need add delay after each MR write. Do you mean?
Setting the DRAM mode register can fail without a delay, so add a 2 μs delay after each MR write.
Where is that documented? Why 2 μs?
https://review.coreboot.org/#/c/32284/1//COMMIT_MSG@11 PS1, Line 11: You also reorder stuff and add comments. That should be separate commits.