[coreboot-gerrit] Change in coreboot[master]: src/mb/google/volteer: workaround for GPIO PM on s0ix entry/exit

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40261 )

Change subject: src/mb/google/volteer: workaround for GPIO PM on s0ix entry/exit
......................................................................

src/mb/google/volteer: workaround for GPIO PM on s0ix entry/exit

Setting the default values for GPIO community power management,
causing issues in detecting tpm interrupts. So to avoid that gpio pm
had to be disabled in devicetree. But for s0ix it is needed. This
patch implements a workaround in asl code to enable gpio pm on s0ix
entry and disable it on s0ix exit.

This patch adds three methods platform specific methods

1. MS0X to enable power management features for GPIO communities on
entry and on exit, it disables them.

2. MPTS to enable power management features for GPIO communities when
preparing to sleep

3. MWAK to disable power management features for GPIO communities on
waking up

BUG=b:148892882
BRANCH=none
TEST="Booted with this change on volteer proto1 and checked for GPIO
community config with debugger"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: If522c82c0069a4bf5738beb73a2b4f11ed6f51d3
---
M src/mainboard/google/volteer/dsdt.asl
A src/mainboard/google/volteer/mainboard.asl
2 files changed, 54 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40261/1

diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
index 640f7cd..ac4b0b9 100644
--- a/src/mainboard/google/volteer/dsdt.asl
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -32,11 +32,16 @@
    		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
    		#include <soc/intel/tigerlake/acpi/southbridge.asl>
    	}
+		/* Mainboard hooks */
+		#include "mainboard.asl"
    }

// Chrome OS specific
    #include <vendorcode/google/chromeos/acpi/chromeos.asl>

+	/* Low power idle table */
+	#include <soc/intel/tigerlake/acpi/lpit.asl>
+
    // Chrome OS Embedded Controller
    Scope (_SB.PCI0.LPCB)
    {
diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl
new file mode 100644
index 0000000..69f5a23
--- /dev/null
+++ b/src/mainboard/google/volteer/mainboard.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <intelblocks/gpio.h>
+
+Method (LOCL, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 6, Local0++)
+	{
+		_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	LOCL (0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from _SB.LPID._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* S0ix Entry */
+		LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	} Else {
+		/* S0ix Exit */
+		LOCL (0)
+	}
+}