[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )

Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
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Patch Set 14:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39538/14/src/soc/intel/skylake/chip... 
File src/soc/intel/skylake/chip.h:

https://review.coreboot.org/c/coreboot/+/39538/14/src/soc/intel/skylake/chip... 
PS14, Line 286: PcieRpAspm
IMO, it's a bad idea to use the same identifier as FSP with a different
encoding. It's easy to confuse, somebody could miss the enum and put the
original FSP values into a devicetree. Beside that, CamelCase doesn't
belong in coreboot.