[coreboot-gerrit] Change in coreboot[master]: mb/google/brya: Configure TCSS OC pins for brya

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52321 )

Change subject: mb/google/brya: Configure TCSS OC pins for brya
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mb/google/brya: Configure TCSS OC pins for brya

TCSS OC pins has not been correctly configured for brya.
This patch fills the value from devicetree to correct the OC pins
mapping

BUG=b:184653645
BRANCH=None
TEST=check if UPD value has been reflected correctly

Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/52321/1

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index d7e2522..92e136c 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -47,6 +47,10 @@
    register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
    register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN

+	register "tcss_usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+	register "tcss_usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"
+	register "tcss_usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"
+
    register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoPci,
    	[PchSerialIoIndexI2C1] = PchSerialIoPci,