[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail: Add MRC SMBus workaround

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44092 )

Change subject: soc/intel/baytrail: Add MRC SMBus workaround
......................................................................

Patch Set 3: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/44092/3/src/soc/intel/baytrail/roms... 
File src/soc/intel/baytrail/romstage/raminit.c:

https://review.coreboot.org/c/coreboot/+/44092/3/src/soc/intel/baytrail/roms... 
PS3, Line 173: spd_buf
> spd_buf[i] ?

See comments on PS1, MRC expects both pointers to be the same (I tested this on Q1900M).

Please add a comment explaining that MRC expects the SPD data to be passed in like that, though. Otherwise, people might be tempted to "fix" this.