[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Allow fine grained control of S0iX states

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44355 )

Change subject: soc/intel/tigerlake: Allow fine grained control of S0iX states
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soc/intel/tigerlake: Allow fine grained control of S0iX states

Expose devicetree parameter to enable/disable each individual substate.

See https://review.coreboot.org/c/coreboot/+/43741 for context.

TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137

Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7
Signed-off-by: [e-mail]
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44355
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 25 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index dc910ff..2da63ed 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -56,6 +56,20 @@
 #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 |	\
    		    FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5)

+/* Bit values for use in LpmStateEnableMask. */
+enum lpm_state_mask {
+	LPM_S0i2_0 = BIT(0),
+	LPM_S0i2_1 = BIT(1),
+	LPM_S0i2_2 = BIT(2),
+	LPM_S0i3_0 = BIT(3),
+	LPM_S0i3_1 = BIT(4),
+	LPM_S0i3_2 = BIT(5),
+	LPM_S0i3_3 = BIT(6),
+	LPM_S0i3_4 = BIT(7),
+	LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
+		     | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
+};
+
 struct soc_intel_tigerlake_config {

/* Common struct containing soc config data required by common code */
@@ -78,6 +92,9 @@

/* Enable S0iX support */
    int s0ix_enable;
+	/* S0iX: Selectively disable individual sub-states, by default all are enabled. */
+	enum lpm_state_mask LpmStateDisableMask;
+
    /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
    uint8_t TcssD3HotDisable;
    /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index a61a025..0a5fbe7 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -204,6 +204,14 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* S0iX: Selectively enable individual sub-states,
+	 * by default all are enabled.
+	 *
+	 * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
+	 * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4
+	 */
+	params->LpmStateEnableMask = LPM_S0iX_ALL & ~config->LpmStateDisableMask;
+
    /*
     * Power Optimizer for DMI and SATA.
     * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0.