Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39477 )
Change subject: mb/google/dedede: Enable Intel Speed Shift Technology ......................................................................
mb/google/dedede: Enable Intel Speed Shift Technology
Enable Intel Speed Shift Technology (ISST) by default. Disable ISST in waddledee and waddledoo variants on early phases.
BUG=b:151281860 TEST=Build and boot the mainboard. Ensure that cpufreq driver to configure P-states is enabled in kernel on boards where board version is provisioned.
Change-Id: Id65d7981501c2f282e564bfc140f8d499d5713e8 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39477 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Aamir Bohra aamir.bohra@intel.com Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/dedede/variants/waddledee/Makefile.inc A src/mainboard/google/dedede/variants/waddledee/variant.c M src/mainboard/google/dedede/variants/waddledoo/Makefile.inc A src/mainboard/google/dedede/variants/waddledoo/variant.c 7 files changed, 59 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, but someone else must approve Aamir Bohra: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index c503a86..fe89527 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -1,11 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h> +#include <bootstate.h> #include <baseboard/variants.h> #include <device/device.h> #include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h>
+__weak void variant_isst_override(void) +{ + /* + * Implement the override only if the board uses very early/initial revisions of + * Silicon. Otherwise nothing to override. + */ +} + +static void mainboard_config_isst(void *unused) +{ + variant_isst_override(); +} + static void mainboard_init(void *chip_info) { const struct pad_config *pads; @@ -37,3 +51,6 @@ .init = mainboard_init, .enable_dev = mainboard_enable, }; + +/* Configure ISST before CPU initialization */ +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, mainboard_config_isst, NULL); diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c891e6e..1b42dfb 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -133,6 +133,9 @@ register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1"
+ # Enable Speed Shift Technology support + register "speed_shift_enable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 3fdc782..5d8355b 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -39,4 +39,7 @@ */ bool variant_mem_is_half_populated(void);
+/* Variant Intel Speed Shift Technology override */ +void variant_isst_override(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index dfb97ba..aaa65e2 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -4,3 +4,5 @@ SPD_SOURCES += empty #0b0001
romstage-y += memory.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledee/variant.c b/src/mainboard/google/dedede/variants/waddledee/variant.c new file mode 100644 index 0000000..ac3cf58 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <ec/google/chromeec/ec.h> + +void variant_isst_override(void) +{ + config_t *cfg = config_of_soc(); + uint32_t board_ver; + + /* Override/Disable ISST in boards where board version is not populated. */ + if (google_chromeec_get_board_version(&board_ver)) + cfg->speed_shift_enable = 0; +} diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index 922c314..11bbbd6 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -4,3 +4,5 @@ SPD_SOURCES += SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0001
romstage-y += memory.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledoo/variant.c b/src/mainboard/google/dedede/variants/waddledoo/variant.c new file mode 100644 index 0000000..ac3cf58 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <ec/google/chromeec/ec.h> + +void variant_isst_override(void) +{ + config_t *cfg = config_of_soc(); + uint32_t board_ver; + + /* Override/Disable ISST in boards where board version is not populated. */ + if (google_chromeec_get_board_version(&board_ver)) + cfg->speed_shift_enable = 0; +}