Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, John Zhao, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39459
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATUON_3 ......................................................................
soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATUON_3
FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3 Configure TcssAuxOri to retimer enabled on the port 2 Type-C port. This setting informs the SoC that a retimer is taking care of SBU orientation therefore it does not need to do any flipping.
The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux orientation settings for the Type-C ports the TGL EDS describes this setting and what each bit represents.
Reference section 3.6.5 in TGL EDS #575681 BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on volteer, Connecting Type-c display should work regardless of Type-c cable orientation.
Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c 2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/39459/4