Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47259 )
Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47259/7//COMMIT_MSG@9 PS7, Line 9: Added change to select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED : is selected in Tigerlake soc Kconfig.
Furquan while I was making code changes, I realized that the change you have made is appropriate. […]
That sounds okay. BTW, as I was reviewing this and following change again I realized that it might be better to do the following since you anyways have to touch both SoC and mainboard Kconfig files:
CL-1: Flip the selection of INTEL_CAR_NEM and INTEL_CAR_NEM_ENHANCED_V2 between mainboard and SoC. i.e. update all TGL boards that are not selecting INTEL_CAR_NEM_ENHANCED_V2 right now to select INTEL_CAR_NEM. And select INTEL_CAR_NEM_ENHANCED_V2 in SoC/Kconfig if INTEL_CAR_NEM is not selected. This will make it easier to flip the NEM enhanced versions at the SoC level without having to make any changes in mainboard in the future. Also, when a board deprecates support for the earlier silicon, it can just drop the selection of INTEL_CAR_NEM. (P.S. You will need to update both volteer and tglrvp).
CL-2: Switch TGL to using INTEL_CAR_NEM_ENHANCED_V1 and select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED is selected. You can add the reasoning in commit message that we are selecting V1 because the SF mask programming required is still being investigated.
Sorry about the back and forth. I think with the above changes, we will make it easier to handle the update of NEM enhanced at the SoC level in the future.
https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG@14 PS10, Line 14: 171601324 This should be b:171601324
https://review.coreboot.org/c/coreboot/+/47259/10//COMMIT_MSG@15 PS10, Line 15: Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache. BRANCH=volteer