Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73875 )
Change subject: soc/amd/mendocino: Add UPDs for DPTC current limits ......................................................................
soc/amd/mendocino: Add UPDs for DPTC current limits
Add UPD vrm_current_limit_mA, vrm_maximum_current_limit_mA, vrm_soc_current_limit_mA for DPTC. Make sure UPD parameterare are set to be aligned.
BUG=b:245942343 BRANCH=none TEST=confirm the UPD parameters has been set correspondingly with the FSP UPD.
Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb Signed-off-by: Patrick Huang patrick.huang@amd.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/73875 Reviewed-by: Matt DeVillier matt.devillier@amd.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/vendorcode/amd/fsp/mendocino/FspmUpd.h 1 file changed, 25 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve
diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index 9f68101..bed13af 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -97,7 +97,10 @@ /* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */ /** Offset 0x04D8**/ uint32_t usb_phy_ptr; /** Offset 0x04DC**/ uint8_t dxio_tx_vboost_enable; - /** Offset 0x04DD**/ uint8_t UnusedUpdSpace2[291]; + /** Offset 0x04DD**/ uint32_t vrm_current_limit_mA; + /** Offset 0x04E1**/ uint32_t vrm_maximum_current_limit_mA; + /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; + /** Offset 0x04E9**/ uint8_t UnusedUpdSpace2[279]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG;