Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30749 )
Change subject: sb/amd/agesa/hudson/Kconfig: Disable XHCI by default, enable only with firmware ......................................................................
Patch Set 4:
Find below comments for Bolton support in leaked KaveriPI tree. At least the following register modifications are missing in vendocode/fam15tn/hudson (which is pre-Bolton but still has two XHCI controllers).
Per vendorcode, 0.14:0 [08] revision >= 0x15 is identified as Bolton where following is done. My lenovo/g505s reports 0x16 here. Now, most of those below do say 'enhance' instead of 'fix' so using hudson vendorcode for bolton hardware may be quite functional.
Be aware, if you come across those leaked KaveriPI or CarrizoPI trees, some of the firmware binaries there suffered CRLF conversions and are corrupted. AFAICS, bolton blob in 3rdparty/blobs matches the one my lenovo/g505s was originally shipped with.
// RPR 8.27 Enhance D3Cold ccu sequencing // RPR 8.28 Set HCIVERSION to 1.0 // RPR 8.29 xHCI 1.0 Sub-Features Supported // RRG 8.30 XHC USB2 Loopback RX SE0 // RRG 8.31 XHC U2IF_Enabled_Quiettermination off // RRG 8.32 XHC S0 BLM Reset Mode // RRG 8.33 Enhance XHC Ent_Flag // RRG 8.34 Enhance TRB Pointer when both MSE and SKIP TRB IOC evt opened // RRG 8.35 LPM Broadcast disable // RRG 8.37 Enhance XHC FS/LS connect // RRG 8.38 Enhance XHC ISOCH td_cmp // RRG 8.39 LPM Clock 5us Select // RRG 8.40 Enhance DPP ERR as XactErr // RRG 8.41 Enhance U2IF PME Enable // RRG 8.42 U2IF S3 Disconnect detection // RRG 8.43 Stream Error Handling // RRG 8.44 FLA Deassert // RRG 8.45 LPM Ctrl Improve // 393674 Enable fix for control transfer error
//8.60 Enhance LPM Host initial L1 Exit
// RRG 8.46 Enhance resume after disconnect // RRG 8.47 Enhance SS HD Detected on Plug-in during S3 // RRG 8.48 Frame Babble Reporting // xHCI Debug Capability // RRG 8.49 DCP Halt RSTSM OFF // RRG 8.50 Enable DCP DPH check // RRG 8.51 DCP LTSSM Inactive to Rxdetect // RRG 8.52 Enhance DCP EP State // RRG 8.53 DCP Remote Wakeup Capable // RRG 8.58 Enable ERDY send once DBC detectes HIT/HOT // RRG 8.59 Block HIT/HOT until service interval done // RRG 8.54 Enhance SS HS detected during S3 // RRG 8.55 Enhance U1 timer (shorten U1 exit response time) // RRG 8.56 Enhance HW LPM U2Entry state // RRG 8.57 Enhance SSIF PME // RPR 8.62 Enable FW enhancement on XHC clock control when memory power saving is disabled // RPR 8.63 U2IF Remote Wake Select // RPR 8.64 HS Data Toggle Error Handling // A1 // UBTS 444589 PIL failures when reset device command hit link td points to invaild trb // UBTS 437021 PME not generated by U2IF logic during S3 shutdown // UBTS 432864 When a USB3 device is disconnected, and connected again, xHC cannot detect it. // UBTS 430710 USB3 port enters compliance state when debug port enabled (0: enable) // UBTS 430715 [DbC] Compatibility issue with 3rd party (I) chip as Host and AMD as Target // UBTS 430708 The second configure endpoint command haven't been executed completely when the port was in L1 // UBTS 428048 [LPM] LPM 2ports interrupt in is ERROR after host initiate L1exit respond a nak in HS // UBTS 428045 LPM packet with incorrect address // UBTS 443139 Buffer overrun during S4 loop // UBTS 419582 LPM arbitration between USB ports // UBTS 429765 USB3.0 ACPI Indirect registers get changed after reboot // UBTS 439658 Black Magic USB 3.0 device when enabled/disabled under windows causes the driver to register disconnect // UBTS SS RX terminations blocked unexpectedly