[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
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Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 139: Enable8254ClockGating
> Looks like these are reserved in the stripped FSP headers, it will need to be added back for this to […]

we will update FSP header by EOD.

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 140: 1
> It looks like if Enable8254ClockGating==0 but .. […]

yes, make sense, will clean for other SOC as well at once