Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38279 )
Change subject: mb/google/dedede: Enable ACPI and add ACPI table ......................................................................
mb/google/dedede: Enable ACPI and add ACPI table
Enable ACPI configuration and add DSDT ACPI table.
BUG=b:144768001 TEST=Build Test
Change-Id: I0aa889cd52bff3e1e9ff7b7b93ec1000045bcfd2 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/dedede/Kconfig A src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/mainboard.c 3 files changed, 52 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38279/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 7c42404..21ba001 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,5 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES select SOC_INTEL_JASPERLAKE
if BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl new file mode 100644 index 0000000..f9bd032 --- /dev/null +++ b/src/mainboard/google/dedede/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <arch/acpi.h> +#include <variant/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/tigerlake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/tigerlake/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> + +} diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 7b02be7..2b1262e 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0-or-later */
+#include <arch/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> @@ -21,9 +22,16 @@ gpio_configure_pads(pads, num); }
+static unsigned long mainboard_write_acpi_tables( + struct device *device, unsigned long current, acpi_rsdp_t *rsdp) +{ + return current; +} + static void mainboard_enable(struct device *dev) { - /* TODO: Enable mainboard */ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = NULL; }
struct chip_operations mainboard_ops = {