Attention is currently required from: Benjamin Doron, Martin L Roth.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79160?usp=email )
Change subject: Documentation: Improve x86_64 ......................................................................
Patch Set 1:
(4 comments)
File Documentation/arch/x86/x86_64.md:
https://review.coreboot.org/c/coreboot/+/79160/comment/8a1c2a09_4601fa65 : PS1, Line 19: * The BIOS region of the SPI flash is memory mapped at reset. haven't exactly looked at the details of how this works on newer AMD SoCs, but there the bootblock is typically already executed from DRAM, so this isn't true in that case
https://review.coreboot.org/c/coreboot/+/79160/comment/25bea93b_a4c7c57a : PS1, Line 107: * Fix running VGA Option ROMs option roms can't currently be run directly when in long mode, since only going to real mode is only implemented from protected mode and not from long mode, but using yabel still works from long mode. unsure how compatible yabel is with option roms in general though
https://review.coreboot.org/c/coreboot/+/79160/comment/28538153_9b60c4c9 : PS1, Line 117: * Place and run code above 4GiB do we really need this? i'd say that we should just keep all code and stack/heap below 4GB
https://review.coreboot.org/c/coreboot/+/79160/comment/6d9e77a2_e262ee08 : PS1, Line 155: * Entering long mode crashes on AMD host platforms.
I don't think this is true anymore. […]
i haven't added the code for switching back to 32 bit mode before calling FSP; that code was already in place. on Picasso i can build coreboot in 64 bit mode and the 32 bit FSP still runs fine. on Cezanne and Mendocino there was some problem that someone else debugged, but i don't remember what the cause and solution was and if the solution has already been put into place. on Genoa, coreboot uses long mode and not protected mode