Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47206 )
Change subject: mb/purism/librem_mini: Update GPIO config ......................................................................
mb/purism/librem_mini: Update GPIO config
Update GPIO config using a fresh dump of inteltool from the vendor (AMI) firmware on a Librem Mini v2, run through intelp2m with parameters '-p cnl -n -ii'
Change-Id: I747415fb9ab7b21943d256d248729cb9e2b4b945 Signed-off-by: Matt DeVillier matt.devillier@puri.sm Reviewed-on: https://review.coreboot.org/c/coreboot/+/47206 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c 1 file changed, 60 insertions(+), 60 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 254510e..3a48dc5 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -38,8 +38,8 @@ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
/* GPP_A7 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A7, 0, DEEP), + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A7, 1, DEEP),
/* GPP_A8 - CLKRUN# */ /* DW0: 0x44000700, DW1: 0x00000000 */ @@ -54,7 +54,7 @@ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
/* GPP_A11 - GPIO */ - /* DW0: 0x80880201, DW1: 0x00000000 */ + /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A11, 1, PLTRST),
/* GPP_A12 - GPIO */ @@ -74,8 +74,8 @@ PAD_CFG_GPO(GPP_A15, 1, PLTRST),
/* GPP_A16 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST), + /* DW0: 0x84000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST),
/* GPP_A17 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -115,9 +115,9 @@ /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
- /* GPP_B2 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* GPP_B2 - VRALERT# */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),
/* GPP_B3 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -167,17 +167,17 @@ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B14, 1, PLTRST),
- /* GPP_B15 - GSPI0_CS0# */ - /* DW0: 0x00000701, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1), + /* GPP_B15 - GPIO */ + /* DW0: 0x80000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST),
/* GPP_B16 - GSPI0_CLK */ /* DW0: 0x84000601, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1),
/* GPP_B17 - GSPI0_MISO */ - /* DW0: 0x44000502, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* DW0: 0x84000502, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B17, NONE, PLTRST, NF1),
/* GPP_B18 - GSPI0_MOSI */ /* DW0: 0x84000601, DW1: 0x00000000 */ @@ -274,8 +274,8 @@ PAD_CFG_GPO(GPP_D7, 1, PLTRST),
/* GPP_D8 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D8, 0, PLTRST), + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D8, 1, PLTRST),
/* GPP_D9 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -294,16 +294,16 @@ PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE),
/* GPP_D13 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D13, 1, RSMRST), + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D13, NONE),
/* GPP_D14 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D14, 1, PLTRST),
/* GPP_D15 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST),
/* GPP_D16 - GPIO */ /* DW0: 0x04000200, DW1: 0x00000000 */ @@ -352,8 +352,8 @@ PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),
/* GPP_F3 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), + /* DW0: 0x84000300, DW1: 0x00003000 */ + PAD_NC(GPP_F3, UP_20K),
/* GPP_F4 - CNV_BRI_DT */ /* DW0: 0x44000700, DW1: 0x00003000 */ @@ -494,20 +494,20 @@ PAD_CFG_GPO(GPP_H13, 1, PLTRST),
/* GPP_H14 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H14, 0, PLTRST), + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST),
/* GPP_H15 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H15, 1, PLTRST),
/* GPP_H16 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H16, 1, RSMRST), + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H16, NONE),
/* GPP_H17 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H17, 1, RSMRST), + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H17, 0, DEEP),
/* GPP_H18 - CPU_C10_GATE# */ /* DW0: 0x44000700, DW1: 0x00000000 */ @@ -518,7 +518,7 @@ PAD_CFG_GPO(GPP_H19, 1, PLTRST),
/* GPP_H20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: 0x84000300, DW1: 0x00000000 */ PAD_NC(GPP_H20, NONE),
/* GPP_H21 - GPIO */ @@ -538,52 +538,52 @@ /* ------- GPIO Group GPD ------- */
/* GPD0 - BATLOW# */ - /* DW0: 0x04000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
/* GPD1 - ACPRESENT */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
/* GPD2 - LAN_WAKE# */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1),
/* GPD3 - PRWBTN# */ - /* DW0: 0x04000702, DW1: 0x00003000 */ - PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
/* GPD4 - SLP_S3# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
/* GPD5 - SLP_S4# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
/* GPD6 - SLP_A# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
/* GPD7 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPD7, 0, RSMRST), + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD7, 0, DEEP),
/* GPD8 - SUSCLK */ - /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
/* GPD9 - SLP_WLAN# */ - /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
/* GPD10 - SLP_S5# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
/* GPD11 - LANPHYPC */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
/* ------- GPIO Community 4 ------- */
@@ -634,8 +634,8 @@ PAD_CFG_GPO(GPP_C10, 0, PLTRST),
/* GPP_C11 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C11, 1, PLTRST), + /* DW0: 0x40100103, DW1: 0x00000000 */ + PAD_CFG_GPI_APIC(GPP_C11, NONE, DEEP, LEVEL, NONE),
/* GPP_C12 - UART1_RXD */ /* DW0: 0x84000603, DW1: 0x00000000 */ @@ -650,8 +650,8 @@ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
/* GPP_C15 - UART1_CTS# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1),
/* GPP_C16 - I2C0_SDA */ /* DW0: 0x84000402, DW1: 0x00000000 */ @@ -776,12 +776,12 @@ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* GPP_E22 - DPPD_CTRLCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E22, NONE, PLTRST, NF1),
/* GPP_E23 - DPPD_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E23, NONE, PLTRST, NF1), };
const struct pad_config *variant_gpio_table(size_t *num)