Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35555 )
Change subject: soc/mediatek/mt8183: Run calibration with multiple frequencies for DVFS switch ......................................................................
Patch Set 12:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/Kc... File src/soc/mediatek/mt8183/Kconfig:
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/Kc... PS12, Line 33: _DUAL_FREQ_K Maybe just call this MT8183_DRAM_DVFS ?
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 1086: dramc_set_broadcast is this a general bug fix?
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 417: setbits_le32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); : setbits_le32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); : setbits_le32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); is this really related to this patch (enable multi-frequency)?
looks more like general fix to me?
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 921: clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); is this a general bug fix?
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 983: [1] is this a general bug fix?
https://review.coreboot.org/c/coreboot/+/35555/12/src/soc/mediatek/mt8183/dr... PS12, Line 1215: 0 is this a general bug fix?