[coreboot-gerrit] Change in coreboot[master]: arch/x86: Add postcar_frame_add_ramcache() API

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34805 )

Change subject: arch/x86: Add postcar_frame_add_ramcache() API
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34805/1/src/arch/x86/postcar_loader... 
File src/arch/x86/postcar_loader.c:

https://review.coreboot.org/c/coreboot/+/34805/1/src/arch/x86/postcar_loader... 
PS1, Line 135: MTRR_TYPE_WRPROT
> You set the MTRR to WRPROT to cache a region that you want to write to?

yeah, WB can't be satisfied option here due to caching issue. (Data region already marked as WB)

This leads into only 2 option WT or WP.

Do you think WT might be better option than WP?

Write protected (WP) — Reads come from cache lines when possible, and read misses cause cache fills.
Writes are propagated to the system bus and cause corresponding cache lines on all processors on the bus to
be invalidated. Speculative reads are allowed.

SDM vol 3a, table 11.2