[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Set controller state to active in uart init

[Usha P (Code Review)]

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34447 )

Change subject: soc/intel/common: Set controller state to active in uart init
......................................................................

soc/intel/common: Set controller state to active in uart init

Set the controller state to D0 during the uart init sequence, this ensures
the controller is up and active.

Signed-off-by: Usha P 
Change-Id: I0187267670e1dea3e1d5e83d0b29967724d6063e
---
M src/soc/intel/common/block/uart/uart.c
1 file changed, 6 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/34447/1

diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 9d820ff..e3ed7c5 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -33,8 +33,11 @@
 extern const struct uart_gpio_pad_config uart_gpio_pads[];
 extern const int uart_max_index;

-static void uart_lpss_init(uintptr_t baseaddr)
+static void uart_lpss_init(uintptr_t baseaddr,struct device *dev)
 {
+	 /* Ensure controller is in D0 state */
+        lpss_set_power_state(dev, STATE_D0);
+
    /* Take UART out of reset */
    lpss_reset_release(baseaddr);

@@ -81,7 +84,7 @@
    /* Enable memory access and bus master */
    pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE);

-	uart_lpss_init(baseaddr);
+	uart_lpss_init(baseaddr,device);
 }

struct device *uart_get_device(void)
@@ -224,7 +227,7 @@

base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF;
    	if (base)
-			uart_lpss_init(base);
+			uart_lpss_init(base,dev);
    }
 }