Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45452 )
Change subject: nb/intel/gm45: Clean up header handling ......................................................................
nb/intel/gm45: Clean up header handling
There's no need to have ACPI guards in `gm45.h`, since the only things the ASL files require are the base address definitions in `memmap.h`. Also, remove the southbridge include from `gm45.h` and place it only in the files that actually require something from it.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45452 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/pcie.c 4 files changed, 4 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index af58e0e..e4d8d66 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include "hostbridge.asl" -#include "../gm45.h" +#include "../memmap.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index e362841..86f71d6 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -2,6 +2,7 @@
#include <stdint.h> #include <device/pci_ops.h> +#include <southbridge/intel/i82801ix/i82801ix.h> #include "gm45.h"
void gm45_early_init(void) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 8be1873..4d8a923 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -3,10 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__
-#include <southbridge/intel/i82801ix/i82801ix.h> - -#ifndef __ACPI__ - #include <stdint.h>
typedef enum { @@ -163,8 +159,6 @@ VCO_5333 = 2, };
-#endif - /* Offsets of read/write training results in CMOS. They will be restored upon S3 resumes. */ #define CMOS_READ_TRAINING 0x80 /* 16 bytes */ @@ -409,8 +403,6 @@
#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */
-#ifndef __ACPI__ - void gm45_early_init(void); void gm45_early_reset(void);
@@ -460,5 +452,4 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp);
-#endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index ce49d62..fd7ce52 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -4,6 +4,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> +#include <southbridge/intel/i82801ix/i82801ix.h>
#include "gm45.h"