Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35170 )
Change subject: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35170/3/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/35170/3/src/soc/intel/skylake/bootb... PS3, Line 59: pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF);
FSP hides P2SB but recently a CB got merged unhiding it again after FSP-S, so this is not true anymore
With "this", I guess you are referring to "this is done early because FSP hides the P2SB in ramstage"? I don't think it matters for this change.
The writes are now done in romstage instead of bootblock, which is more sound. And even then, since only FSP-S seems to hide the P2SB, it is still early enough.
Since this is a long thread on an older patchset, I am marking it as resolved. Please make a new comment on a more current patchset instead of making this thread even longer.