[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/braswell/smbus.c: Add support for i2c mode block write

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33225 )

Change subject: soc/intel/braswell/smbus.c: Add support for i2c mode block write
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Patch Set 9:

(1 comment)

https://review.coreboot.org/#/c/33225/9/src/soc/intel/braswell/smbus.c 
File src/soc/intel/braswell/smbus.c:

https://review.coreboot.org/#/c/33225/9/src/soc/intel/braswell/smbus.c@57 
PS9, Line 57: 	status = do_smbus_block_write(smbase, addr, offset, bytes, buf);
> You really should not touch any of the SMBUS IO-mapped registers before checking that the host is no […]

I agree that that is not much information Braswell SMBus registers. (The IO mapped registers are not decribed in Intel EDS #547871, only the memory mapped!).
The Fig 14 page 11 is the correct the SMBus controller format. However the SMBus controller uses the registers <SMBXNITADD> <SMBHSTDAT1> <SMBBLKDAT> ... <SMBBLKDAT> to compose this format.

Will verify if mod of PCI registers after check not busy will work.