Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 42:
(2 comments)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/7cc65b11_f1bbd1d4
PS42, Line 274: const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i];
Shouldn't there be a check here to ensure that the device is enabled? i.e. […]
Done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/a4f74951_b05bb8fe
PS42, Line 8: #define PCIE_RP(x) ((x) - 1)
Add a comment stating that PCIe root port numbers are 1-based, but we use 0-based indexes for the co […]
Done
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