Attention is currently required from: yuchi.chen@intel.com.
Shuo Liu has posted comments on this change by yuchi.chen@intel.com. ( https://review.coreboot.org/c/coreboot/+/85012?usp=email )
Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR ......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/itss/itss.c:
https://review.coreboot.org/c/coreboot/+/85012/comment/9340fffc_a52ebd6c?usp... : PS5, Line 140: uint16_t pir = pcr_read16(PID_ITSS, itss_soc_get_pir(dev)); Will itss_soc_get_pir use offsets other than PCR_ITSS_PIR?