Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4041
-gerrit
commit 7295008eb923ba6d6d6b8716c93b4307c9ac4ec6 Author: Rudolf Marek r.marek@assembler.cz Date: Tue Nov 12 16:46:47 2013 +0100
Asus F2A85-M: Fix S3 memory power cut-off
The power to memory is lost during the the suspend, activate the 3VSBSW# which switches the power during S3 suspend sequence.
As a result resuming from suspend to RAM works now, but now the GPP ports of the Hudson southbridge are gone after resume from S3. The devices 15.0 and 15.1 are disabled (decode as ffff) and therefore anything behind them too [1].
[1] http://www.coreboot.org/pipermail/coreboot/2013-November/076620.html fam15tn hudson PCIe GPP ports off after resume
Change-Id: Id953313ee4400a03a2ad8ca09e39a5e0d5f92524 Signed-off-by: Rudolf Marek r.marek@assembler.cz --- src/mainboard/asus/f2a85-m/romstage.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 5d01bb4..031bb50 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -90,6 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sbxxx_enable_48mhzout(); it8712f_kill_watchdog(); it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + it8712f_enable_3vsbsw(); console_init();
/* turn on secondary smbus at b20 */