[coreboot-gerrit] Change in ...coreboot[master]: mediatek/mt8183: Add infra group DCM setting

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31977 )

Change subject: mediatek/mt8183: Add infra group DCM setting
......................................................................

mediatek/mt8183: Add infra group DCM setting

Add infra group DCM (Dynamic Clock Management) settings,
which slows down OR gate clocks while hardware is in idle state.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui.

Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2
Signed-off-by: Weiyi Lu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31977
Tested-by: build bot (Jenkins) 
Reviewed-by: Julius Werner 
Reviewed-by: You-Cheng Syu 
---
M src/soc/mediatek/mt8183/include/soc/pll.h
M src/soc/mediatek/mt8183/pll.c
2 files changed, 15 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved
  You-Cheng Syu: Looks good to me, but someone else must approve

diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h
index 2a72e2c..3807e00 100644
--- a/src/soc/mediatek/mt8183/include/soc/pll.h
+++ b/src/soc/mediatek/mt8183/include/soc/pll.h
@@ -270,4 +270,13 @@
    SPI_HZ		= MAINPLL_D5_D2_HZ,
 };

+enum {
+	DCM_INFRA_BUS_MASK = 0x40907ffb,
+	DCM_INFRA_BUS_ON = 0x40904203,
+	DCM_INFRA_MEM_ON = 0x1 << 27,
+	DCM_INFRA_P2PRX_MASK = 0xf,
+	DCM_INFRA_PERI_MASK = 0xf03ffffb,
+	DCM_INFRA_PERI_ON = 0xf03f83e3,
+};
+
 #endif /* SOC_MEDIATEK_MT8183_PLL_H */
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index 07ce660..5368077 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -344,6 +344,12 @@

/* enable infrasys DCM */
    setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
+	clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl,
+		DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON);
+	setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON);
+	clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK);
+	clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl,
+		DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON);

/* enable [11] for change i2c module source clock to TOPCKGEN */
    setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11);