[coreboot-gerrit] Change in coreboot[master]: vc/mediatek/mt8195: Improve DRAM driver

[Rex-BC Chen (Code Review)]

Attention is currently required from: Ryan Chuang.
Hello Ryan Chuang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/56104

to review the following change.

Change subject: vc/mediatek/mt8195: Improve DRAM driver
......................................................................

vc/mediatek/mt8195: Improve DRAM driver

Improve settings of duty calibration.

Signed-off-by: Ryan Chuang 
Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
M src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/56104/1

diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
index cea83a0..286e9a0 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
@@ -14804,9 +14804,15 @@
 #endif
 #endif
     {
+        U8 u1ChannelIdx;
+        U8 u1backup_channel = vGetPHY2ChannelMapping(p);
+
         #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
         if(p->femmc_Ready==1)
         {
+            for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++){
+                vSetPHY2ChannelMapping(p, u1ChannelIdx);
+
             DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]);
             DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]);
             #if __LP5_COMBO__
@@ -14816,6 +14822,8 @@
             DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM);
             DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ);
             #endif
+            }
+            vSetPHY2ChannelMapping(p, u1backup_channel);

vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K);
             return;
diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
index a40f290..d27d7ea 100644
--- a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
+++ b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h
@@ -123,7 +123,7 @@
 #else
 #define ENABLE_EYESCAN_GRAPH 1
 #endif
-#define EYESCAN_GRAPH_CATX_VREF_STEP 1  // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
+#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U  // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868
 #define EYESCAN_GRAPH_RX_VREF_STEP 2
 #define EYESCAN_RX_VREF_RANGE_END 128   //field is 6 bit, but can only use 0~63,7bit ->127
 #define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF    10