[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel: separate slp-s0 residency counter frequency in LPIT table

[Sukumar Ghorai (Code Review)]

Attention is currently required from: Jakub Czapiga, Paul Menzel, Subrata Banik.

Hello Jakub Czapiga, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/78177?usp=email

to look at the new patch set (#7).

Change subject: soc/intel: separate slp-s0 residency counter frequency in LPIT table
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soc/intel: separate slp-s0 residency counter frequency in LPIT table

Intel platforms use Low Power Idle Table (LPIT) to enumerate platform
Low Power Idle states. There are two types of low power residencies
 a) CPU PKG C10 - read via MSR (Function fixed hardware interface)
 b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped IO

Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_I...,
section 2.2.1: value of 0 indicates that counter runs at TSC frequency.

Ref. Intel 64 and IA-32 Architectures Software Developer’s Manual (Vol 4)
MSR 0x632: PC10 residency counter is at same frequency as the TSC.
Whereas slp_s0 residency counter running in different frequency.

BUG=b:300440936
TEST=check kernel cpuidle sysfs are created after kernel boot
  cat /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
  cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us

Change-Id: Ibde764551a21b9aecb1c269948f4823548294711
Signed-off-by: Sukumar Ghorai 
---
M src/include/acpi/acpi.h
M src/soc/intel/common/block/acpi/lpit.c
2 files changed, 4 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/78177/7