Attention is currently required from: Nico Huber, Paul Menzel.
Reagan has posted comments on this change by Reagan. ( https://review.coreboot.org/c/coreboot/+/82458?usp=email )
Change subject: mb/razer/blade_stealth_kbl: add panel_cfg ......................................................................
Patch Set 14:
(1 comment)
File src/mainboard/razer/blade_stealth_kbl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82458/comment/26c98a58_66d83f9d?usp... : PS13, Line 163: .backlight_off_delay_ms = 5000, /* T12 */
Alas, the VBT values are not in *ms*. I think it's 1/10th of a ms (most […]
Done. You are right, it is in 100us. At src/soc/intel/skylake/graphics.c, the ms number is multiplied by 10. Annoyingly, `intel_reg` does not know these registers exist on Gen7+ - I had to manually enter the register address. I also checked the stock firmware, and interestingly the registers are the same as on the doc. Additionally, to get the same register values as the stock firmware `down_delay_ms` would need to be 50 and `cycle_delay_ms` 500. Why could this be, despite all VBIOS tables from the stock firmware having the values I used?