Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29016
Change subject: amd/stoneyridge: Fix PmControl register size in SMI handler ......................................................................
amd/stoneyridge: Fix PmControl register size in SMI handler
The AMD implementation of this register is only 16 bits. Change the source accordingly.
TEST=Suspend/Resume a Grunt several times
Change-Id: Ib900468cc1c790fa7d57bb6faa91aee012173f7a Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/29016/1
diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index eeedba7..8985257 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -122,13 +122,13 @@
static void sb_slp_typ_handler(void) { - uint32_t pm1cnt, pci_ctrl, reg32; - uint16_t reg16; + uint32_t pci_ctrl, reg32; + uint16_t pm1cnt, reg16; uint8_t slp_typ, rst_ctrl;
/* Figure out SLP_TYP */ - pm1cnt = inl(pm_acpi_pm_cnt_blk()); - printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", pm1cnt); + pm1cnt = inw(pm_acpi_pm_cnt_blk()); + printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); slp_typ = acpi_sleep_from_pm1(pm1cnt);
/* Do any mainboard sleep handling */ @@ -196,7 +196,7 @@ } /* if (IS_ENABLED(CONFIG_ELOG_GSMI)) */
/* Reissue Pm1 write */ - outl(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk()); + outw(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk()); hlt(); } }