Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47251 )
Change subject: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN ......................................................................
mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
Add strings for M.2 keying and number of PCIe lanes.
Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880 Signed-off-by: Matt DeVillier matt.devillier@puri.sm --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/47251/1
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index e02586c..1a1c466 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -197,7 +197,7 @@ register "PcieRpLtrEnable[7]" = "1" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (WLAN)" "SlotDataBusWidth1X" end device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10