Hello build bot (Jenkins), Raul Rangel, David Guckian, Patrick Rudolph, Lee Leahy, Tim Wawrzynczak, Vanessa Eusebio, Angel Pons, Huang Jin, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44549
to look at the new patch set (#8).
Change subject: memory_info: add max_speed_mts and configured_speed_mts ......................................................................
memory_info: add max_speed_mts and configured_speed_mts
ddr_frequency is ambiguous and is interpreted differently in several places. Instead of renaming this field, this deprecates it and adds two new fields with unambiguous naming, max_speed_mts and configured_speed_mts. smbios.c falls back to using ddr_frequency when either of these fields are 0.
The same value was being used for both configured memory speed and max memory speed in SMBIOS type 17, which is not accurate when configured speed is not the max speed.
BUG=b:167218112 TEST=Boot ezkinil and observe dmidecode -t17 dmidecode -t17 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present.
Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 3200 MT/s Manufacturer: Unknown (0) Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 2400 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown
Change-Id: Iaa75401f9fc33642dbdce6c69bd9b20f96d1cc25 Signed-off-by: Rob Barnes robbarnes@google.com --- M src/arch/x86/smbios.c M src/include/memory_info.h M src/soc/amd/picasso/dmi.c 3 files changed, 27 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44549/8