[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy/variant/nocturne: set GPP_C19 to NF1

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/28867

Change subject: mb/google/poppy/variant/nocturne: set GPP_C19 to NF1
......................................................................

mb/google/poppy/variant/nocturne: set GPP_C19 to NF1

GPP_C19 was not being set as the code was incorrectly setting
GPP_C16 instead, so this change sets C19 to NF1.

Initialize GPP_E3 to a no connect.

BUG=b:117124878
TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and
verify that i2c transactions work for the left SAR sensor.

Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb
Signed-off-by: Nick Vaccaro 
---
M src/mainboard/google/poppy/variants/nocturne/gpio.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28867/1

diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index 15a97c3..7724bc3 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -151,7 +151,7 @@
    /* C18 : I2C1_SDA ==> PCH_I2C1_DISPLAY_SAR_SDA */
    PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
    /* C19 : I2C1_SCL ==> PCH_I2C1_DISPLAY_SAR_SCL */
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
    /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
    PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
    /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
@@ -217,6 +217,8 @@
    /* E2  : SATAXPCIE2 ==> BT_DISABLE_L */
    PAD_CFG_GPO(GPP_E2, 1, DEEP),
    /* E3  : CPU_GP0 ==> NC */
+	PAD_CFG_NC(GPP_E3),
+	/* E3  : DEVSLP0 ==> NC */
    PAD_CFG_NC(GPP_E4),
    /* E5  : SATA_DEVSLP1 ==> NC */
    PAD_CFG_NC(GPP_E5),