[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad

[Johnny Li (Code Review)]

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42956 )

Change subject: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad
......................................................................

mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad

This change updates scl_lcnt,scl_hcnt,scl_hcnt value for I2C5 to bring the bus frequency
closer to 400kHz.

BUG=b:157999726
TEST= Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li 
Change-Id: Ia9c6159565fc5c28ccb3c3f9fb4b2838cde273a0
---
M src/mainboard/google/volteer/variants/volteer2/overridetree.cb
1 file changed, 44 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42956/1

diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
index 24b869c..7319047 100644
--- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
@@ -161,5 +161,49 @@
    			end
    		end
    	end # PMC
+                	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | Audio                     |
+	#| I2C1              | Touchscreen               |
+	#| I2C2              | WLAN, SAR0                |
+	#| I2C3              | Camera, SAR1              |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+                        .speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 163,
+				.scl_hcnt = 75,
+				.sda_hold = 36,
+			},
+		},
+	}"
    end
 end