Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28771 )
Change subject: amd/stoneyridge: Add ASL helper for AOAC PwrGood Control ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/28771/1/src/soc/amd/stoneyridge/acpi/sb_pci0... File src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl:
https://review.coreboot.org/#/c/28771/1/src/soc/amd/stoneyridge/acpi/sb_pci0... PS1, Line 642:
Not very clear. Apparently this code only executes something (HW wise) if Arg0 is bit5.
I agree. I'd meant to go back and figure out what AMD was trying to say, and forgot to. Looks like
/* * Helper... * Arg0: bit to set or clear * Arg1: 0: clear bit[Arg0], non-0: set bit[Arg0] */