[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add PCIe root port wake sources to elog

[Furquan Shaikh (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47398 )

Change subject: soc/intel/alderlake: Add PCIe root port wake sources to elog
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Patch Set 6: Code-Review+2