Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33225 )
Change subject: soc/intel/braswell/smbus.c: Add support for i2c mode block write
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Patch Set 9:
I have APL/SKL/CFL boards here with an 24LC256, so I should
be able to write some test patterns. Then we could also say
if these platforms behave as documented.
Scratch that, the EEPROM is attached to another I2C controller.
But one could do the same with SPDs, in theory ;)
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