Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45259 )
Change subject: sb/intel/bd82x6x: Factor out ME finalization function ......................................................................
sb/intel/bd82x6x: Factor out ME finalization function
The only difference between ME7 and ME8 is that the latter returns an acknowledgment value, which we should read out. The rest is the same.
Change-Id: Icf9004467c3cca4185b45ccd92822f1574ef1efb Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 3 files changed, 59 insertions(+), 95 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/45259/1
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 3876b02..854698b 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -27,30 +27,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-/* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful\n"); - return 0; -} - /* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) { @@ -134,7 +110,31 @@
#ifdef __SIMPLE_DEVICE__
-static void intel_me7_finalize_smm(void) +/* Send END OF POST message to the ME */ +static int intel_me7_send_eop(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) { + printk(BIOS_ERR, "ME: END OF POST message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: END OF POST message successful\n"); + return 0; +} + +void intel_me_finalize_smm(void) { struct me_hfs hfs; u32 reg32; @@ -156,7 +156,17 @@ return;
/* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); + const u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID); + switch (did) { + case 0x1c3a: + intel_me7_send_eop(); + break; + case 0x1e3a: + intel_me8_send_eop(); + break; + default: + printk(BIOS_ERR, "No EOP handler for ME %04x.\n", did); + }
/* Make sure IO is disabled */ pci_and_config16(PCH_ME_DEV, PCI_COMMAND, @@ -166,21 +176,6 @@ RCBA32_OR(FD2, PCH_DISABLE_MEI1); }
-void intel_me_finalize_smm(void) -{ - u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID); - switch (did) { - case 0x1c3a: - intel_me7_finalize_smm(); - break; - case 0x1e3a: - intel_me8_finalize_smm(); - break; - default: - printk(BIOS_ERR, "No finalize handler for ME %04x.\n", did); - } -} - #else
/* Determine the path that we should take based on ME status */ diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index f6cd96b..8dd34bc 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -257,7 +257,8 @@ int intel_early_me_init_done(u8 status);
void intel_me_finalize_smm(void); -void intel_me8_finalize_smm(void); + +int intel_me8_send_eop(void);
typedef struct { u32 major_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index d47c1da..fa51fd7 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -27,33 +27,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif
-/* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - u32 eop_ack; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __func__); - if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); - return 0; -} - static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -127,36 +100,31 @@
#ifdef __SIMPLE_DEVICE__
-void intel_me8_finalize_smm(void) +/* Send END OF POST message to the ME */ +int intel_me8_send_eop(void) { - struct me_hfs hfs; - u32 reg32; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + };
- update_mei_base_address(); + u32 eop_ack;
- /* S3 path will have hidden this device already */ - if (!is_mei_base_address_valid()) - return; + /* Send request and wait for response */ + printk(BIOS_NOTICE, "ME: %s\n", __func__); + if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { + printk(BIOS_ERR, "ME: END OF POST message failed\n"); + return -1; + }
- /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, ®32, sizeof(u32)); - - /* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || - hfs.operation_mode != ME_HFS_MODE_NORMAL) - return; - - /* Try to send EOP command so ME stops accepting other commands */ - mkhi_end_of_post(); - - /* Make sure IO is disabled */ - pci_and_config16(PCH_ME_DEV, PCI_COMMAND, - ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); + printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); + return 0; }
#else /* !__SIMPLE_DEVICE__ */