[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede: Add SD card support

[Varshit B Pandya (Code Review)]

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39237 )

Change subject: mb/google/dedede: Add SD card support
......................................................................

mb/google/dedede: Add SD card support

1. Configure SD card GPIOs.
2. Set SD card power polarity and card detect configs.

Change-Id: I90c8ceb85ada23718ff7b6fd7013317c818dd532
Signed-off-by: Pandya, Varshit B 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/dedede/variants/baseboard/gpio.c
2 files changed, 13 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/39237/1

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index d82dfc7..69899ac 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -106,6 +106,10 @@
    # Enable EMMC HS400 mode
    register "ScsEmmcHs400Enabled" = "1"

+	# SD card configuration
+	register "sdcard_cd_gpio" = "VGPIO_39"
+	register "SdCardPowerEnableActiveHigh" = "1"
+
    # Display related UPDs
    # Select eDP for port A
    register "DdiPortAConfig" = "1"
@@ -167,7 +171,7 @@
    		register "wake" = "GPE0_PME_B0"
    		device pci 14.3 on  end # CNVi wifi
    	end
-		device pci 14.5 off end # SDCard
+		device pci 14.5 on end # SDCard
    	device pci 15.0 on  end # I2C 0
    	device pci 15.1 on  end # I2C 1
    	device pci 15.2 on  end # I2C 2
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c
index 2b93159..753f7ba 100644
--- a/src/mainboard/google/dedede/variants/baseboard/gpio.c
+++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c
@@ -272,21 +272,19 @@
    PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),

/* G0  : SD_CMD */
-	PAD_NC(GPP_G0, NONE),
+	PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1),
    /* G1  : SD_DATA0 */
-	PAD_NC(GPP_G1, NONE),
+	PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1),
    /* G2  : SD_DATA1 */
-	PAD_NC(GPP_G2, NONE),
+	PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1),
    /* G3  : SD_DATA2 */
-	PAD_NC(GPP_G3, NONE),
+	PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1),
    /* G4  : SD_DATA3 */
-	PAD_NC(GPP_G4, NONE),
-	/* G5  : SD_CD_ODL */
-	PAD_NC(GPP_G5, NONE),
+	PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1),
+	/* G5  : SD_CD# */
+	PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
    /* G6  : SD_CLK */
-	PAD_NC(GPP_G6, NONE),
-	/* G7  : SD_SDIO_WP */
-	PAD_NC(GPP_G7, NONE),
+	PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),

/* H0  : WWAN_PERST */
    PAD_NC(GPP_H0, NONE),