[coreboot-gerrit] Change in coreboot[master]: mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42874 )

Change subject: mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42874/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42874/4//COMMIT_MSG@7 
PS4, Line 7: mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL
A bit off-topic..

What do each of H1_ PCH_ INT_ and ODL mean in this context?

The GPIO #defines are without _ODL in soc/amd. Some boards use CR50_IRQ here?

google/cheza and google/trogdor uses name GPIO_H1_AP_INT here?