Attention is currently required from: Anil Kumar K, Krishna P Bhat D, Rizwan Qureshi.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74874?usp=email )
Change subject: soc/intel/cse: Check PSR bit before issuing PSR backup command ......................................................................
Patch Set 7:
(4 comments)
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/74874/comment/88a8beb9_797d75da : PS6, Line 1106:
the command needs to be run after CSE is in RW .. so called it after we switch to RW.
Ack kindly write that in comment section of the helper function, this API is only supported w/ CSE is RW.
This is being called in the case when we do a CSE downgrade. Will not be invoked in regular boot flow . so should not have boot time impact
that is okay but at worst case, we should know for sure the boot time impact. I'm afraid that, the CSE is taking longer time without any reason.
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/74874/comment/2d89070e_90a70db1 : PS7, Line 1078: first check if PSR is supported by the SKU nit:
``` Check if SoC has support for PSR feature (typically PSR feature is only supported by vpro SKU) ```
https://review.coreboot.org/c/coreboot/+/74874/comment/640171e5_87153130 : PS7, Line 1086: /* PSR is not supported in this SKU */ you don't need this comment
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/74874/comment/1d499222_fbf2f3d0 : PS7, Line 43: #define ME_FW_FEATURE_PSR BIT(5) align with line 42 (need two space may be ?)