Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )
Change subject: sc7180: QSIP SPI NOR addressing mode
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38542/5//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/38542/5//COMMIT_MSG@9
PS5, Line 9: Putting SPI NOR 3 byte addressing mode as it is not supporting 4 byte addressing mode.
The text width limit is 75 characters.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/38542
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d
Gerrit-Change-Number: 38542
Gerrit-PatchSet: 5
Gerrit-Owner: mturney mturney
mturney@codeaurora.org
Gerrit-Reviewer: Sajida Bhanu
sbhanu@codeaurora.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Aaron Durbin
adurbin@chromium.org
Gerrit-CC: Julius Werner
jwerner@chromium.org
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Tue, 28 Jan 2020 15:10:04 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment