Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40002 )
Change subject: mb/google/cyan: Switch eMMC and SD from ACPI to PCI mode ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40002/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40002/1//COMMIT_MSG@10 PS1, Line 10: SeaBIOS requires : an onerous workaround Do you have a reference for that?
https://review.coreboot.org/c/coreboot/+/40002/1//COMMIT_MSG@13 PS1, Line 13: from ACPI mode to PCI mode. Re-flow for 72/75 characters?
https://review.coreboot.org/c/coreboot/+/40002/1//COMMIT_MSG@14 PS1, Line 14: Any idea, what the reasoning for ACPI mode was from Chromium OS? Will the OS set this up for itself?