[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Cache cbmem and stage cache in romstage

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37200 )

Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage
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nb/intel/sandybridge: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
3 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/1

diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 0502b50..1745b98 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -20,6 +20,7 @@
    select CPU_INTEL_MODEL_206AX
    select HAVE_DEBUG_RAM_SETUP
    select INTEL_GMA_ACPI
+	select ROMSTAGE_CACHED_CBMEM

if NORTHBRIDGE_INTEL_SANDYBRIDGE

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index c13ae37..441844e 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -19,6 +19,7 @@
 #include <commonlib/region.h>
 #include <bootmode.h>
 #include <cf9_reset.h>
+#include <cpu/x86/mtrr.h>
 #include <string.h>
 #include <arch/cpu.h>
 #include <device/mmio.h>
@@ -422,6 +423,7 @@

report_memory_config();

+	setup_romstage_wb_cbmem_cache();
    cbmem_was_inited = !cbmem_recovery(s3resume);
    if (!fast_boot)
    	save_timings(&ctrl);
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 29c766a..9e70fc1 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -17,6 +17,7 @@
 #include <console/usb.h>
 #include <bootmode.h>
 #include <cf9_reset.h>
+#include <cpu/x86/mtrr.h>
 #include <string.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
@@ -451,6 +452,7 @@
    	hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32));
    }

+	setup_romstage_wb_cbmem_cache();
    cbmem_was_initted = !cbmem_recovery(s3resume);
    if (!s3resume)
    	save_mrc_data(&pei_data);