Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31951 )
Change subject: device/pciexp_device: Add set_L1_ss_latency() for pciexp device ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/#/c/31951/1/src/device/pciexp_device.c File src/device/pciexp_device.c:
https://review.coreboot.org/#/c/31951/1/src/device/pciexp_device.c@470 PS1, Line 470: PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 | The values you set should be parameters to this function, as you cannot assume them to be the same for all hardware. Thus, this function reduces to a single PCI configuration write, and basically just aliases pci_write_config32(), so little point defining it like this.
https://review.coreboot.org/#/c/31951/1/src/include/device/pciexp.h File src/include/device/pciexp.h:
https://review.coreboot.org/#/c/31951/1/src/include/device/pciexp.h@12 PS1, Line 12: Is there some relation between realtime and register value? Maybe change _VALUE to _3140US if not.
https://review.coreboot.org/#/c/31951/1/src/soc/intel/broadwell/pcie.c File src/soc/intel/broadwell/pcie.c:
https://review.coreboot.org/#/c/31951/1/src/soc/intel/broadwell/pcie.c@a655 PS1, Line 655: Just use the new _3140US defines here.